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DI[7:0]

CI2

CI3

CLKIN

PDB

Serializer Deserializer

CI1

Graphic

Processor

Channel Link II

1 Pair / AC Coupled

DS92LV2421 DS92LV2422

100 ohm STP Cable

PASS

DDIO

PDB

SCL

SDA

RFB

VODSEL

DeEmph

BISTEN

LOCK

ID[x]

DAP DAP

CMF

100 nF 100 nF

SCL

SDA

ID[x]

STRAP pins

not shown

RIN+

RIN-

DOUT+

DOUT-

Optional Optional

(1.8V or 3.3V)(1.8V or 3.3V)

1.8V

DDIO

DDn

ASIC/FPGA

24-bit RGB

Display

ASIC/FPGA

DI[15:8]

DI[23:16]

DO[7:0]

CO2

CO3

CLKOUT

CO1

DO[15:8]

DO[23:16]

Video

Imager

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS92LV2421

DS92LV2422

SNLS321C –MAY 2010–REVISED MAY 2016

DS92LV242x 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

1 Features

• 24-Bit Data, 3-Bit Control, 10- to 75-MHz Clock

• AC-Coupled STP Interconnect Cable up to 10 m

• Integrated Terminations on Serializer and

Deserializer

• At-Speed Link BIST Mode and Reporting Pin

• Optional I

C-Compatible Serial Control Bus

• Power-Down Mode Minimizes Power Dissipation

• 1.8-V or 3.3-V Compatible LVCMOS I/O Interface

• –40° to 85°C Temperature Range

• >8-kV HBM

• Serializer (DS92LV2421)

– Data Scrambler for Reduced EMI

– DC-Balance Encoder for AC Coupling

– Selectable Output VOD and Adjustable

De-emphasis

• Deserializer (DS92LV2422)

– Fast Random Data Lock; No Reference Clock

Required

– Adjustable Input Receiver Equalization

– LOCK (Real-Time Link Status) Reporting Pin

– EMI Minimization on Output Parallel Bus

(SSCG)

– Output Slew Control (OS)

2 Applications

• Embedded Videos and Displays

• Medical Imaging and Factory Automation

• Office Automation (Printers and Scanners)

• Security and Video Surveillance

• General-Purpose Data Communication

3 Description

The DS92LV242x chipset translates a parallel 24–bit

LVCMOS data interface into a single high-speed CML

serial interface with embedded clock information. This

single serial stream eliminates skew issues between

clock and data, reduces connector size, and reduces

interconnect cost for transferring a 24-bit or less bus

over FR-4 printed-circuit board backplanes and

balanced cables. In addition, the DS92LV242x

chipset also features a 3-bit control bus for slow

speed signals. This allows for video and display

applications with up to 24 bits per pixel (RGB).

Programmable transmit de-emphasis, receive

equalization, on-chip scrambling, and DC balancing

enables longer distance transmission over lossy

cables and backplanes. The DS92LV2422

automatically locks to incoming data without an

external reference clock or special sync patterns,

providing easy plug-and-go operation. EMI is

minimized by the use of low voltage differential

signaling, receiver drive strength control, and spread

spectrum clocking capability.

The DS92LV242x chipset is programmable though an

C interface as well as through pins. A built-in, at-

speed BIST feature validates link integrity and may

be used for system diagnostics. The DS92LV2421 is

offered in a 48-pin WQFN, and the DS92LV2422 is

offered in a 60-pin WQFN package. Both devices

operate over the full industrial temperature range of

–40°C to 85°C.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DS92LV2421 WQFN (48) 7.00 mm × 7.00 mm

DS92LV2422 WQFN (60) 9.00 mm × 9.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Block Diagram

DS92LV2421

DS92LV2422

SNLS321C –MAY 2010–REVISED MAY 2016

www.ti.com

Product Folder Links: DS92LV2421 DS92LV2422

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications....................................................... 10

6.1 Absolute Maximum Ratings .................................... 10

6.2 ESD Ratings............................................................ 10

6.3 Recommended Operating Conditions..................... 10

6.4 Thermal Information................................................ 11

6.5 Electrical Characteristics – Serializer DC ............... 11

6.6 Electrical Characteristics – Deserializer DC ........... 12

6.7 Electrical Characteristics – DC and AC Serial Control

Bus........................................................................... 13

6.8 Timing Requirements – DC and AC Serial Control

Bus........................................................................... 13

6.9 Timing Requirements – Serializer for CLKIN.......... 13

6.10 Timing Requirements – Serial Control Bus........... 14

6.11 Switching Characteristics – Serializer................... 14

6.12 Switching Characteristics – Deserializer............... 15

6.13 Typical Characteristics.......................................... 21

7 Detailed Description............................................ 22

7.1 Overview ................................................................. 22

7.2 Functional Block Diagrams ..................................... 22

7.3 Feature Description................................................. 23

7.4 Device Functional Modes........................................ 37

7.5 Register Maps......................................................... 38

8 Application and Implementation ........................ 41

8.1 Application Information............................................ 41

8.2 Typical Applications ................................................ 42

9 Power Supply Recommendations...................... 46

9.1 Power-Up Requirements and PDB Pin................... 46

10 Layout................................................................... 47

10.1 Layout Guidelines ................................................. 47

10.2 Layout Example .................................................... 49

11 Device and Documentation Support ................. 51

11.1 Device Support...................................................... 51

11.2 Documentation Support ........................................ 51

11.3 Related Links ........................................................ 51

11.4 Community Resource............................................ 51

11.5 Trademarks........................................................... 51

11.6 Electrostatic Discharge Caution............................ 51

11.7 Glossary................................................................ 52

12 Mechanical, Packaging, and Orderable

Information ........................................................... 52

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2013) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Updated thermal characteristic values based on latest simulation data ............................................................................. 11

• Changed deserializer LVCMOS DC and supply current specification test conditions based on latest production tests .... 12

• Changed I

test condition for V

at V

DDIO

= 3.3 V to 3 mA ............................................................................................... 12

• Changed max value of Deserializer V

to 0.45 V .............................................................................................................. 12

• Changed test condition parameter for V

Serial Control Characteristic ............................................................................ 13

• Changed RPU = 10 kΩ condition for the Serial Control Bus Characteristics of t

and t

................................................... 13

• Added notes for serializer and deserializer switching characteristics verified by characterization ...................................... 14

• Added corresponding pins for deserializer t

CLH

and t

CHL

parameter..................................................................................... 15

• Added test condition to t

deserializer parameter ............................................................................................................. 15

• Changed corrected units for deserializer lock time and delay parameter ........................................................................... 15

• Added serial stream and video control signal filter waveform to Feature Description ........................................................ 23

• Changed "NA" and "Disable" term in Table 5 and Table 6 to "Off" ..................................................................................... 28

• Changed output states to correct values based on OSS_SEL and PDB configuration in Table 7 ..................................... 29

• Added details for Deserializer Map Select strap pin configuration ...................................................................................... 33

• Added clarification on the state of deserializer outputs during BIST mode operation.......................................................... 33

• Added statement to set input to low when entering BIST mode with DS90C241 or DS90UR241 ..................................... 33

• Added note that ID[X] cannot be tied to VSS, as only four device addresses are supported ............................................. 35

• Added RID tolerance and tablenote that RID ≠ 0 Ω to set ID[X] ......................................................................................... 35

• Changed statement that CONFIG settings can also by programmed via register .............................................................. 37

Not to scale

DAP

36 DI91DI22

37DI10 24 VODSEL

35 DI82DI23

38DI11 23 De-Emph

34 DI73CI2

39DI12 22 VDDTX

33 DI64CI3

40DI13 21 PDB

32 DI55CI1

41DI14 20 DOUT+

31 BISTEN6ID[x]

42DI15 19 DOUT-

30 VDDIO7VDDL

43DI16 18 RES2

29 DI48SCL

44DI17 17 VDDHS

28 DI39SDA

45DI18 16 RES1

27 DI210CLKIN

46DI19 15 RES0

26 DI111RFB

47DI20 14 VDDP

25 DI012CONFIG[0]

48DI21 13 CONFIG[1]

DS92LV2421

DS92LV2422

SNLS321C –MAY 2010–REVISED MAY 2016

www.ti.com

Product Folder Links: DS92LV2421 DS92LV2422

(1) G = Ground, I = Input, O = Output, and P = Power

(2) 1= HIGH, 0 = LOW

5 Pin Configuration and Functions

RHS Package

48-Pin WQFN

Top View

Pin Functions: DS92LV2421 (Serializer)

TYPE

(1)

DESCRIPTION

(2)

NAME NO.

LVCMOS PARALLEL INTERFACE

DI[7:0]

34, 33, 32,

29, 28, 27,

26, 25

Parallel interface data input pins, LVCMOS with pulldown.

For 8-bit RED display: DI7 = R7 – MSB, DI0 = R0 – LSB.

DI[15:8]

42, 41, 40,

39, 38, 37,

36, 35

Parallel interface data input pins, LVCMOS with pulldown.

For 8-bit GREEN display: DI15 = G7 – MSB, DI8 = G0 – LSB.

DI[23:16]

2, 1, 48, 47,

46, 45, 44,

Parallel interface data input pins, LVCMOS with pulldown.

For 8-bit BLUE display: DI23 = B7 – MSB, DI16 = B0 – LSB.

CI1 5 I

Control signal input, LVCMOS with pulldown.

For display or video application: CI1 = Data enable input.

Control signal pulse width must be 3 clocks or longer to be transmitted when the Control

signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2

transitions per 130 clocks regardless of the control signal filter setting.

CI2 3 I

Control signal input, LVCMOS with pulldown.

For display or video application: CI2 = Horizontal sync input.

Control signal pulse width must be 3 clocks or longer to be transmitted when the control

signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2

transitions per 130 clocks regardless of the control signal filter setting.

DS92LV2421

DS92LV2422

www.ti.com

SNLS321C –MAY 2010–REVISED MAY 2016

Product Folder Links: DS92LV2421 DS92LV2422

Pin Functions: DS92LV2421 (Serializer) (continued)

TYPE

(1)

DESCRIPTION

(2)

NAME NO.

CI3 4 I

Control signal input, LVCMOS with pulldown.

For display or video application: CI3 = Vertical sync input.

CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is

130 clock cycles wide.

CLKIN 10 I

Clock input, LVCMOS with pulldown.

Latch or data strobe edge set by RFB pin.

CONTROL AND CONFIGURATION

PDB 21 I

Power-down mode input, LVCMOS with pulldown.

PDB = 1, serializer is enabled (normal operation).

Refer to Power-Up Requirements and PDB Pin.

PDB = 0, serializer is powered down. When the serializer is in the power-down state, the

driver outputs (DOUT±) are both logic high, the PLL is shutdown, IDD is minimized. Control

Registers are RESET.

VODSEL 24 I

Differential driver output voltage select (this can also be control by I

C register access),

LVCMOS with pulldown.

VODSEL = 1, LVDS VOD is ±420 mV, 840 mV

p-p

(typical) — long cable or de-emphasis

apps.

VODSEL = 0, LVDS VOD is ±280 mV, 560 mV

p-p

(typical) — short cable (no de-emphasis),

low power mode.

De-Emph 23 I

De-emphasis control (this can also be controlled by I

C register access), analog with pullup.

De-emphasis = open (float) - disabled.

To enable de-emphasis, tie a resistor from this pin to GND or control through register (see

Table 3).

RFB 11 I

Clock input latch or data strobe edge select (this can also be controlled by I

C register

access), LVCMOS with pulldown.

RFB = 1, parallel interface data and control signals are latched on the rising clock edge.

RFB = 0, parallel interface data and control signals are latched on the falling clock edge.

CONFIG[1:0] 13, 12 I

LVCMOS with pulldown.

00: Control Signal Filter DISABLED.

01: Control Signal Filter ENABLED.

10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q-Q1.

11: Reverse compatibility mode to interface with the DS90C124.

ID[X] 6 I

C serial control bus device ID address select (optional), analog.

Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 11).

SCL 8 I

C serial control bus clock input (optional), LVCMOS.

SCL requires an external pullup resistor to V

DDIO

SDA 9 I/O

C serial control bus data input or output (optional), LVCMOS (open drain).

SDA requires an external pullup resistor V

DDIO

BISTEN 31 I

BIST mode (optional), LVCMOS with pulldown.

BISTEN = 0, BIST is disabled (normal operation).

BISTEN = 1, BIST is enabled.

RES[2:0] 18, 16, 15 I Reserved (tie low), LVCMOS with pulldown.

CHANNEL-LINK II – CML SERIAL INTERFACE

DOUT+ 20 O

Noninverting output, CML.

The output must be AC-coupled with a 0.1-µF capacitor.

DOUT– 19 O

Inverting output, CML.

The output must be AC-coupled with a 0.1-µF capacitor.

剩余62页未读，继续阅读

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