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DS92LV8028

www.ti.com

SNLS152I –NOVEMBER 2001–REVISED APRIL 2013

DS92LV8028 8 Channel 10:1 Serializer

Check for Samples: DS92LV8028

1

FEATURES

DESCRIPTION

The DS92LV8028 integrates eight serializer devices

2

• All 8 Channels Synchronous to One Parallel

into a single chip. The DS92LV8028 can

Clock Rate, from 25 to 66 MHz

simultaneously serialize up to eight 10-bit data

• Duplicates Function of Multiple DS92LV1021

streams. The 10-bit parallel inputs are LVTTL signal

and '1023 10-bit Serializer Devices

levels. The serialized outputs are LVDS signals with

extra drive current for point-to-point and lightly loaded

• Serializes from One to Eight 10-bit Parallel

multidrop applications. Each serializer block in the

Inputs into Data Streams with Embedded

DS92LV8028 operates independently by using

Clock

strobes from a single shared PLL.

• Eight 5 mA Modified Bus LVDS Outputs that

The DS92LV8028 uses a single +3.3V power supply

are Capable to Drive Double Terminations

with a typical power dissipation of 740mW (3.3V /

• @Speed Test - PRBS Generation to Check

PRBS / 66 MHz). Each serializer channel has a

LVDS Transmission Path to SCAN921224 or

unique power down control to further conserve power

SCAN921260

consumption.

• On Chip Filtering for PLL

For high-speed LVDS serial data transmission, line

• 740mW Typ Power Dissipation (Loaded, PRBS,

quality is essential, thus the DS92LV8028 includes an

66MHz, 3.3V)

@SPEED TEST function. Each Serializer channel

has the ability internally generated a PRBS data

• High Impedance Inputs and Outputs on Power

pattern. This pattern is received by specific

Off

deserializers (SCAN921224) which have the

• Single Power Supply at +3.3V (+/-10%)

complement PRBS verification circuit. The

• 196-Pin NFBGA Package

deserializer checks the data pattern for bit errors and

reports any errors on the test verification pins on the

• JTAG Pins Reserved for Next Version of

deserializer.

Device

• Industrial Temperature Range Operation: -40

For additional information - please see the

Applications Information section in this datasheet.

to +85 °C

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS92LV8028

www.ti.com

SNLS152I –NOVEMBER 2001–REVISED APRIL 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)(2)

Supply Voltage (V

CC

) −0.3V to +4V

LVCMOS/LVTTL Input Voltage −0.3V to (V

CC

+0.3V)

Bus LVDS Driver Output Voltage −0.3V to +3.9V

Bus LVDS Output Short Circuit Duration 10ms

θ

JA

196 NFBGA: 34°C/W

Package Thermal Resistance θ

JC

196 NFBGA: 8°C/W

Storage Temperature −65°C to +150°C

Junction Temperature +125°C

Lead Temperature (Soldering, 10 seconds) +225°C

ESD Rating (HBM) ±3.0kV

Reliability Information Transistor Count: 37.5k

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply

that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage (V

CC

) 3.0 3.3 3.6 V

Operating Free Air Temperature (T

A

) −40 +25 +85 °C

Clock Rate 25 66 MHz

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

LVCMOS/LVTTL DC Specifications

V

IH

High Level Input Voltage 2.0 V

CC

V

DINn[0-9], TCLK,

MS_PWDN, PWDNn,

V

IL

Low Level Input Voltage GND 0.8 V

SYNCn, DEN,

V

CL

Input Clamp Voltage I

CL

= −18 mA −0.87 −1.5 V

BIST_ACT,

BIST_SEL<0:3>

(3)

I

IN

Input Current V

IN

= 0V or 3.6V −10 +/− 1 +10 μA

Bus LVDS DC Specifications

Over recommended operating supply and temperature unless otherwise specified.

(1) Typical values are given for V

CC

= 3.3V and T

A

= +25°C.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

except VOD, and ΔVOD which are differential voltages.

(3) BIST_SEL pins are pull-up internally.

Product Folder Links: DS92LV8028

DS92LV8028

www.ti.com

SNLS152I –NOVEMBER 2001–REVISED APRIL 2013

Serializer Timing Requirements for TCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

t

TCP

Transmit Clock Period 15.15 40 ns

Transmit Clock High

t

TCIH

40 50 60 %

Time

Transmit Clock Low

t

TCIL

See Figure 3 TCLK 40 50 60 %

Time

TCLK Input Transition

t

CLKT

3 6 ns

Time

t

JIT

TCLK Input Jitter 80 ps

rms

(1) Typical values are given for V

CC

= 3.3V and T

A

= +25°C.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

except VOD, and ΔVOD which are differential voltages.

Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

Bus LVDS Low-to-High

t

LLHT

198 236 400 ps

R

L

= 100Ω

Transition Time

C

L

=10pF to GND

(3)

DOn+, DOn-

Bus LVDS High-to-Low

Figure 2

t

LHLT

115 232 400 ps

Transition Time

DIN (0-9) Setup to

t

DIS

1.5 ns

R

L

= 100Ω,

TCLK

C

L

=10pF to GND DINn(0-9), TCLK

DIN (0-9) Hold from

Figure 4

t

DIH

1.5 ns

TCLK

DO ± HIGH to

t

HZD

5.7 12 ns

TRI-STATE Delay

DO ± LOW to TRI-

t

LZD

6.9 12 ns

R

L

= 100Ω,

STATE Delay

C

L

=10pF to GND DOn+, DOn-, DEN

DO ± TRI-STATE to

Figure 5

t

ZHD

6.2 12 ns

HIGH Delay

DO ± TRI-STATE to

t

ZLD

5.8 12 ns

LOW Delay

SYNC Pattern Delay,

t

SPD

4*t

TCP

5*t

TCP

ns

TCLK, SYNCn,

Figure 8

R

L

= 100Ω

DOn+, DOn-,

C

L

=10pF to GND

Serializer PLL Lock

MS_PWDN

t

PLD

510*t

TCP

513*t

TCP

ns

Time, Figure 6

R

L

= 100Ω

DINn(0-9), TCLK,

t

SD

Serializer Delay C

L

=10pF to GND t

TCP

+ 3.2 t

TCP

+ 3.5 t

TCP

+ 6 ns

DOn+, DOn-

Figure 7

Individual Channel TCLK, DOn+, DOn-,

t

ICR

60*t

TCP

63*t

TCP

70*t

TCP

ns

Power up Time PWDNn

R

L

= 100Ω,

C

L

=10pF to GND

TCLK, DOn+, DOn-,

t

MCR

Master Power up Time 510*t

TCP

513*t

TCP

ns

MS_PWDN Figure 6

@Speed Test Enable

t

STE

R

L

= 100Ω 10*t

TCP

ns

BIST_ACT,

Time

BIST_SEL (0:3),

@Speed Test Disable

TCLK, DOn+, DOn-

t

STD

R

L

= 100Ω 7*t

TCP

ns

Time

25 MHz 130 ps

Channel to Channel R

L

= 100Ω,

t

SKEW

Skew C

L

=10pF to GND

66 MHz 80 ps

(1) Typical values are given for V

CC

= 3.3V and T

A

= +25°C.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

except VOD, and ΔVOD which are differential voltages.

(3) t

LLHT

, t

LHLT

, t

DJIT

and t

RJIT

specifications are ensured by design using statistical analysis.

Product Folder Links: DS92LV8028

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