DS92LV0411, DS92LV0412
www.ti.com
SNLS331B –MAY 2010–REVISED APRIL 2013
DS92LV0411 / DS92LV0412 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS
Parallel Interface
Check for Samples: DS92LV0411, DS92LV0412
1
FEATURES
DESCRIPTION
The DS92LV0411 (serializer) and DS92LV0412
2
• 5-Channel (4 data + 1 clock) Channel Link
(deserializer) chipset translates a Channel Link LVDS
LVDS Parallel Interface Supports 24-bit Data
video interface (4 LVDS Data + LVDS Clock) into a
3-bit Control at 5 – 50 MHz
high-speed serialized interface over a single CML
• AC Coupled STP Interconnect up to 10 Meters
pair.
in Length
The DS92LV0411/DS92LV0412 enables applications
• Integrated Serial CML Terminations
that currently use the popular Channel Link or
• AT–SPEED BIST Mode and Status Pin
Channel Link style devices to seamlessly upgrade to
an embedded clock interface to reduce interconnect
• Optional I2C Compatible Serial Control Bus
cost or ease design challenges. The parallel LVDS
• Power Down Mode Minimizes Power
interface also reduces FPGA I/O pins, board trace
Dissipation
count and alleviates EMI issues, when compared to
• 1.8V or 3.3V Compatible Control Pin Interface
traditional single-ended wide bus interfaces.
• >8 kV ESD (HBM) Protection
Programmable transmit de-emphasis, receive
• -40° to +85°C Temperature Range equalization, on-chip scrambling and DC balancing
enables longer distance transmission over lossy
SERIALIZER – DS92LV0411
cables and backplanes. The Deserializer
• Data Scrambler for Reduced EMI
automatically locks to incoming data without an
• DC–Balance Encoder for AC Coupling
external reference clock or special sync patterns,
providing easy “plug-and-go” operation.
• Selectable Output VOD and Adjustable De-
Emphasis
The DS92LV0411 and DS92LV0412 are
programmable though an I2C interface as well as by
DESERIALIZER – DS92LV0412
pins. A built-in AT-SPEED BIST feature validates link
• Random Data Lock; No Reference Clock
integrity and may be used for system diagnostics.
Required
The DS92LV0411 and DS92LV0412 can be used
• Adjustable Input Receiver Equalization
interchangeably with the DS92LV2411 or
• EMI Minimization on Output Parallel Bus
DS92LV2412. This allows designers the flexibility to
(Spread Spectrum Clock Generation and LVDS
connect to the host device and receiving devices with
VOD Select)
different interface types, LVDS or LVCMOS.
APPLICATIONS
• Embedded Video and Display
• Machine Vision, Industrial Imaging, Medical
Imaging
• Office Automation — Printers, Scanners,
Copiers
• Security and Video Surveillance
• General purpose data communication
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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