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LVCMOS
DC Balance Encoder
Parallel-to-Serial
TxIN0
Control
TxCLKIN
Pre-Emp
Serial-to-Parallel
Control
Decoding, Alignment
LVCMOS
CDR/PLL
Cable Deskew
High-Speed
Serial Data
TxOUT0+
TxOUT0 -
TxOUT1+
TxOUT1 -
RxIN1 +
RxIN0+
RxIN0 -
RxIN1 -
PLL
Tx - SERIALIZER
TxIN15
TxIN16
TxIN31
RxOUT0
RxCLKOUT
RxOUT15
RxOUT16
RxOUT31
100:differential pairs
Rx - DESERIALIZER
MODE
BISTEN
R_FB
PDB
VSEL
PRE
REN
R_FB
PDB
LOCK
BIST
BIST
DS92LV3221, DS92LV3222
www.ti.com
SNLS319C –OCTOBER 2009–REVISED APRIL 2013
DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer
Check for Samples: DS92LV3221, DS92LV3222
1
FEATURES
APPLICATIONS
2
• Wide Operating Range Embedded Clock
• Industrial Imaging (Machine-vision) and
SER/DES Control
– Up to 32-bit Parallel LVCMOS Data • Security and Surveillance Cameras and
Infrastructure
– 20 to 50 MHz Parallel Clock
• Medical Imaging
– Up to 1.6 Gbps Application Data Paylod
• Simplified Clocking Architecture
DESCRIPTION
– No Separate Serial Clock Line
The DS92LV3221 (SER) serializes a 32-bit data bus
– No Reference Clock Required
into 2 embedded clock LVDS serial channels for a
data payload rate up to 1.6 Gbps over cables such as
– Receiver Locks to Random Data
CATx, or backplanes FR-4 traces. The companion
• On-chip Signal Conditioning for Robust Serial
DS92LV3222 (DES) deserializes the 2 LVDS serial
Connectivity
data channels, de-skews channel-to-channel delay
– Transmit Pre-Emphasis
variations and converts the LVDS data stream back
into a 32-bit LVCMOS parallel data bus.
– Data Randomization
– DC-Balance Encoding
On-chip data Randomization/Scrambling and DC
balance encoding and selectable serializer Pre-
– Receive Channel Deskew
emphasis ensure a robust, low-EMI transmission over
– Supports up to 10m CAT-5 at 1.6Gbps
longer, lossy cables and backplanes. The
• Integrated LVDS Terminations
Deserializer automatically locks to incoming data
without an external reference clock or special sync
• Built-in AT-SPEED BIST for End-To-End
patterns, providing an easy “plug-and-lock” operation.
System Testing
• AC-Coupled Interconnect for Isolation and
By embedding the clock in the data payload and
including signal conditioning functions, the Channel-
Fault Protection
Link II SerDes devices reduce trace count, eliminate
• > 4KV HBM ESD Protection
skew issues, simplify design effort and lower
• Space-Saving 64-pin TQFP Package
cable/connector cost for a wide variety of video,
• Full Industrial Temperature Range: -40° to
control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may
+85°C
be used for system diagnostics.
BLOCK DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.