TI-ADC32RF54.pdf

ADC32RF5x Dual Channel 14-bit 2.6 to 3-GSPS RF Sampling Data Converter

1 Features

• 14-Bit, dual channel 2.6/3.0-GSPS ADC

• Noise spectral density:

– NSD = -156 dBFS/Hz (no AVG, 3 GSPS)

– NSD = -159 dBFS/Hz (2x AVG , 3 GSPS)

– NSD = -161 dBFS/Hz (4x AVG, 2.6 GSPS)

• Single core (non-interleaved) ADC architecture

• Aperture jitter: 50 fs

– SFDR HD2,3: 75 dBc

– SFDR worst spur: 90 dBFS

• Spectral performance (f

IN

= 1.8 GHz, -1 dBFS):

– 2x internal averaging

– SNR: 61.6 dBFS

– SFDR HD2,3: 70 dBc

– SFDR worst spur: 90 dBFS

• Input fullscale: 1.1/1.35 Vpp (2/3.5 dBm)

• Code error rate (CER): 10

– Up to four DDC per ADC channel

– Complex output: 4x to 128x decimation

– 48-bit NCO phase coherent frequency hopping

– Fast frequency hopping: < 1 us

• Power consumption: 2.2 W/channel (2x AVG)

• Power supplies: 1.8 V, 1.2 V

2 Applications

• Phased array radar

• Spectrum analyzer

• Software defined radio (SDR)

3 Description

The ADC32RF5x is a single core 14-bit, 2.6

GSPS to 3 GSPS, dual channel analog to digital

signal-to-noise ratio (SNR) and delivers a noise

spectral density of -156 dBFS/Hz. Using additional

internal ADCs along with on-chip signal averaging, the

noise density improves to -161 dBFS/Hz.

Each ADC channel can be connected to a quad-band

digital down-converter (DDC) using a 48-bit NCO

which supports phase coherent frequency hopping.

Using the GPIO pins for NCO frequency control,

frequency hopping can be achieved in less than 1 µs.

The ADC32RF54 and ADC32RF55 supports the

The power efficient ADC architecture consumes 1.8

W/ch at 3 Gsps and provides power scaling with lower

sampling rates.

(1) For all available packages, see the package option

ADC32RF55 3.0 GSPS

ADC32RF54 2.6 GSPS

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

without notice.

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

7.2 Functional Block Diagram......................................... 27

7.3 Feature Description...................................................28

7.4 Device Functional Modes..........................................57

7.5 Programming............................................................ 58

V

J

115 °C

–65 150 °C

(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

A

Operating free-air temperature –40 85 °C

J

Operating junction temperature 105

(1)

°C

(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.