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ADC08DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 8-bit, RF-

Sampling Analog-to-Digital Converter (ADC)

1 Features

• ADC core:

– 8-bit resolution

– Up to 10.4 GSPS in single-channel mode

– Up to 5.2 GSPS in dual-channel mode

• Performance specifications:

– Noise floor (–20 dBFS, V

= 1 V

PP-DIFF

• Dual-channel mode: –143.4 dBFS/Hz

• Single-channel mode: –146.2 dBFS/Hz

– ENOB (dual channel, F

= 2.4 GHz, TYP): 7.8

Bits

• Buffered analog inputs with V

CMI

of 0 V:

– Analog input bandwidth (–3 dB): 8.1 GHz

– Usable input frequency range: > 10 GHz

– Full-scale input voltage (V

, default): 0.8 V

• Noiseless aperture delay (t

) adjustment:

– Precise sampling control: 19-fs Step

– Simplifies synchronization and interleaving

– Temperature and voltage invariant delays

• Easy-to-use synchronization features:

– Automatic SYSREF timing calibration

– Timestamp for sample marking

• JESD204C serial data interface:

– Maximum lane rate: 17.16 Gbps

– Support for 64b/66b and 8b/10b encoding

– 8b/10b modes are JESD204B compatible

• Peak RF Input Power (Diff): +26.5 dBm (+ 27.5

dBFS, 560x fullscale power)

• Programmable FIR filter for equalization

• Power consumption: 3.8 W

• Power supplies: 1.1 V, 1.9 V

2 Applications

• Oscilloscopes and wideband digitizers

• Communications testers (802.11ad, 5G)

• Electronic warfare (SIGINT, ELINT)

• Satellite communications (SATCOM)

• RF-sampling software-defined radio (SDR)

• Spectrometry

3 Description

The ADC08DJ5200RF device is an RF-sampling,

giga-sample, analog-to-digital converter (ADC) that

directly samples input frequencies from DC to above

10 GHz. The ADC08DJ5200RF can be configured as

a dual-channel, 5.2 GSPS ADC or single-channel,

10.4 GSPS ADC. Support of a useable input

frequency range of up to 10 GHz enables direct RF

sampling of L-band, S-band, C-band, and X-band for

frequency agile systems.

The ADC08DJ5200RF uses a high-speed JESD204C

output interface with up to 16 serialized lanes

supporting up to 17.16 Gbps line rate. Deterministic

latency and multi-device synchronization is supported

through JESD204C subclass-1. The JESD204C

interface can be configured to trade-off line rate and

number of lanes. Both 8b/10b and 64b/66b data

encoding schemes are supported. 64b/66b encoding

supports forward error correction (FEC) for improved

bit error rates. The interface is backwards compatible

with JESD204B receivers.

Innovative synchronization features, including

noiseless aperture delay adjustment and SYSREF

windowing, simplify system design for multi-channel

applications. A programmable FIR filter allows on-chip

equalization.

Device Information

PART NUMBER PACKAGE

(1)

BODY SIZE (NOM)

ADC08DJ5200RF FCBGA (144) 10.00 mm × 10.00 mm

(1) For all available packages, see the package option

addendum at the end of the data sheet.

ADC08DJ5200RF Block Diagram

ADC08DJ5200RF

SLVSEO1 – AUGUST 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 8

6.1 Absolute Maximum Ratings ....................................... 8

6.2 ESD Ratings .............................................................. 8

6.3 Recommended Operating Conditions ........................9

6.4 Thermal Information ...................................................9

6.5 Electrical Characteristics: DC Specifications ........... 10

6.6 Electrical Characteristics: Power Consumption ....... 12

6.7 Electrical Characteristics: AC Specifications

(Dual-Channel Mode) ................................................. 13

6.8 Electrical Characteristics: AC Specifications

(Single-Channel Mode) .............................................. 18

6.9 Timing Requirements ...............................................24

6.10 Switching Characteristics .......................................25

6.11 Typical Characteristics............................................ 28

7 Detailed Description......................................................49

7.1 Overview................................................................... 49

7.2 Functional Block Diagram......................................... 50

7.3 Feature Description...................................................51

7.4 Device Functional Modes..........................................73

7.5 Programming............................................................ 87

7.6 SPI Register Map......................................................89

8 Application Information Disclaimer........................... 143

8.1 Application Information........................................... 143

8.2 Typical Applications................................................ 143

8.3 Initialization Set Up................................................. 145

9 Power Supply Recommendations..............................146

9.1 Power Sequencing..................................................147

10 Layout.........................................................................148

10.1 Layout Guidelines................................................. 148

10.2 Layout Example.................................................... 149

11 Device and Documentation Support........................152

11.1 Device Support......................................................152

11.2 Documentation Support........................................ 152

11.3 Receiving Notification of Documentation Updates 153

11.4 Support Resources............................................... 153

11.5 Trademarks........................................................... 153

11.6 Electrostatic Discharge Caution............................ 153

11.7 Glossary................................................................ 153

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

August 2021 * Initial release.

ADC08DJ5200RF

SLVSEO1 – AUGUST 2021

www.ti.com

2 Submit Document Feedback

Product Folder Links: ADC08DJ5200RF

Table 5-1. Pin Functions

I/O DESCRIPTION

NAME NO.

AGND

A1, A2, A3,

A6, A7, B2,

B3, B4, B5,

B6, B7, C6,

D1, D6, E1,

E6, F2, F3, F6,

G2, G3, G6,

H1, H6, J1, J6,

L2, L3, L4, L5,

L6, L7, M1,

M2, M3, M6,

—

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit

board.

BG C3 O

Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited

capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be

left disconnected if not used.

CALSTAT F7 O

Foreground calibration status output or device alarm output. Functionality is programmed through

CAL_STATUS_SEL. This pin can be left disconnected if not used.

CALTRIG E7 I

Foreground calibration trigger input. This pin is only used if hardware calibration triggering is

selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG.

Tie this pin to GND if not used.

CLK+ F1 I

Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-

coupled to this input for best performance. In single-channel mode, the analog input signal is

sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled

on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination

and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is

set to 0.

CLK– G1 I

Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best

performance.

DA0+ E12 O

High-speed serialized data output for channel A, lane 0, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DA0– F12 O

High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left

disconnected if not used.

DA1+ C12 O

High-speed serialized data output for channel A, lane 1, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DA1– D12 O

High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left

disconnected if not used.

DA2+ A10 O

High-speed serialized-data output for channel A, lane 2, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DA2– A11 O

High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left

disconnected if not used.

DA3+ A8 O

High-speed serialized-data output for channel A, lane 3, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DA3– A9 O

High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left

disconnected if not used.

DA4+ E11 O

High-speed serialized data output for channel A, lane 4, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DA4– F11 O

High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left

disconnected if not used.

DA5+ C11 O

High-speed serialized data output for channel A, lane 5, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

ADC08DJ5200RF

SLVSEO1 – AUGUST 2021

www.ti.com

4 Submit Document Feedback

Product Folder Links: ADC08DJ5200RF

Table 5-1. Pin Functions (continued)

I/O DESCRIPTION

NAME NO.

DA5– D11 O

High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left

disconnected if not used.

DA6+ B10 O

High-speed serialized data output for channel A, lane 6, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DA6– B11 O

High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left

disconnected if not used.

DA7+ B8 O

High-speed serialized data output for channel A, lane 7, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DA7– B9 O

High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left

disconnected if not used.

DB0+ H12 O

High-speed serialized data output for channel B, lane 0, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB0– G12 O

High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left

disconnected if not used.

DB1+ K12 O

High-speed serialized data output for channel B, lane 1, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB1– J12 O

High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left

disconnected if not used.

DB2+ M10 O

High-speed serialized data output for channel B, lane 2, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB2– M11 O

High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left

disconnected if not used.

DB3+ M8 O

High-speed serialized data output for channel B, lane 3, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB3– M9 O

High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left

disconnected if not used.

DB4+ H11 O

High-speed serialized data output for channel B, lane 4, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB4– G11 O

High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left

disconnected if not used.

DB5+ K11 O

High-speed serialized data output for channel B, lane 5, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB5– J11 O

High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left

disconnected if not used.

DB6+ L10 O

High-speed serialized data output for channel B, lane 6, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB6– L11 O

High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left

disconnected if not used.

DB7+ L8 O

High-speed serialized data output for channel B, lane 7, positive connection. This differential

output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

DB7– L9 O

High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left

disconnected if not used.

www.ti.com

ADC08DJ5200RF

SLVSEO1 – AUGUST 2021

Submit Document Feedback

Product Folder Links: ADC08DJ5200RF

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