TI-DS90UR916Q-Q1.pdf

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G[7:0] 20, 21, 22, I, STRAP, GREEN Parallel Interface Data Output Pins (MSB = 7, LSB = 0)

B[7:0] 9, 10, 11, I, STRAP, BLUE Parallel Interface Data Output Pins (MSB = 7, LSB = 0)

HS 8 O, LVCMOS Horizontal Sync Output

In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video

control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control

PCLKs.

DE 6 O, LVCMOS Data Enable Output

In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video

control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control

Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2

transitions per 130 PCLKs.

PCLK 5 O, LVCMOS Pixel Clock Output

In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Strobe

edge set by RFB function.

DE and PCLK output states are controlled by OSS_SEL (See Table 5). May be used as Link

Status or to flag when Video Data is active (ON/OFF).

For a High State, use a 10 kΩ pull up to V

; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon

power-up and set device configuration. Pin Number listed along with shared RGB Output name in square brackets.

CONFIG[1:0] 10 [B6], STRAP Operating Modes — Pin or Register Control

9 [B7] I, LVCMOS These pins determine the DS90UR916’s operating mode and interfacing device.

w/ pull-down CONFIG[1:0] = 00: Interfacing to DS90UR905, Control Signal Filter DISABLED

CONFIG[1:0] = 01: Interfacing to DS90UR905, Control Signal Filter ENABLED

CONFIG[1:0] = 10: Interfacing to DS90UR241

CONFIG[1:0] = 11: Interfacing to DS90C241

w/ pull-down OS_PCLK = 0, normal (default)

OS_DATA 14 [B3] STRAP Data Output Slew Select — Pin or Register Control

I, LVCMOS OS_DATA = 1, increased DATA slew

w/ pull-down OS_DATA = 0, normal (default)

(1) 1 = HIGH, 0 = LOW.

OP_LOW 42 PASS STRAP Outputs held Low when LOCK = 1 — Pin or Register Control

I, LVCMOS NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS

w/ pull-down STRAP FUNCTION

OP_LOW = 1: all outputs are held LOW during power up until released by programming

w/ pull-down OSS_SEL is used in conjunction with PDB to determine the state of the outputs when

inactive. (See Table 5).

RFB 18 [B1] STRAP Pixel Clock Output Strobe Edge Select — Pin or Register Control

I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.

w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.

EQ[3:0] 20 [G7], STRAP Receiver Input Equalization — Pin or Register Control

OSC_SEL[2:0] 26 [G2], STRAP Oscillator Select — Pin or Register Control

w/ pull-down

PDB 59 I, LVCMOS Power Down Mode Input

w/ pull-down PDB = 1, Des is enabled (normal operation).

Refer to POWER UP REQUIREMENTS AND PDB PIN in the Applications Information

Section.

PDB = 0, Des is in power-down.

When the Des is in the power-down state, the LVCMOS output state is determined by

Open Drain SDA requires an external pull-up resistor to V

.

BISTEN 44 I, LVCMOS BIST Enable Input — Optional

w/ pull-down BISTEN = 1, BIST is enabled

BISTEN = 0, BIST is disabled

w/ pull-down

NC 1, 15, 16, Not Connected