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FPD-Link解串器

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100Q STP Cable

FPD-Link Display Interface

RGB Display

720p

24-bit Color Depth

DS90UB927Q-Q1

Serializer

DS90UB928Q-Q1

Deserializer

FPD-Link III

1 Pair/AC Coupled

DDIO

(1.8V or 3.3V)

FPD-Link

RxIN1+/-

RxCLKIN+/-

RxIN2+/-

RxIN0+/-

RxIN3+/-

TxOUT1+/-

TxCLKOUT+/-

TxOUT2+/-

TxOUT0+/-

TxOUT3+/-

DDIO

(1.8V or 3.3V)

HOST

Graphics

Processor

DOUT+

DOUT-

RIN+

RIN-

SDA

SCL

I2S

MCLK

DD33

(3.3V)

DD33

(3.3V)

MODE_SEL

BISTEN

LFMODE

MAPSEL

PDB

OSS_SEL

OEN

BKWD

REPEAT

LFMODE

MAPSEL

IDx

SDA

SCL

LOCK

PASS

PDB

INTB

I2S

INTB_IN

IDx

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

Reference

Design

DS90UB928Q-Q1

ZHCSDB5B –MARCH 2013–REVISED JANUARY 2015

DS90UB928Q-Q1 5MHz 至至 85MHz 24 位位彩彩色色 FPD-Link III 至至 FPD-Link

解解串串器器，，具具有有双双向向控控制制通通道道

1 特特性性 3 说说明明

• 双向控制通道接口，可连接到 I

C 兼容串行控制总

DS90UB928Q-Q1 解串器与 DS90UB925Q-Q1 或

线

DS90UB927Q-Q1 串行器配套使用，可针对汽车信息

• 低电磁干扰 (EMI) FPD-Link 视频输出

娱乐系统内的内容受保护数字视频的安全分发提供一套

• 支持高清 (720p) 数字视频

解决方案。。该解串器借助嵌入式时钟（由单信号对

• 支持 RGB888 + VS，HS，DE 和 I2S 音频

(FPD-Link III) 提供）将高速串行化接口数据转换为四

• 支持 5MHz、85MHz 像素时钟

个低压差分信令 (LVDS) 数据/控制流、一个 LVDS 时

• 多达 4 个针对环绕立体声应用的 I2S 数字音频输出

钟对 (FPD-Link) 以及 I2S 音频数据。 FPD-Link III 串

• 4 条具有 2 个专用引脚的双向通用输入输出 (GPIO)

行总线方案支持通过单个差分链路实现高速正向通道数

通道

据传输和低速全双工反向通道通信。通过单个差分对

• 通过 1.8V 或 3.3V 兼容 LVCMOS I/O 接口实现

整合音频、视频和和控制数据可减小互连线尺寸和重

3.3V 单电源运行

量，同时还消除了偏差问题并简化了系统设计。

• 长达 10 米的交流耦合屏蔽双绞线 (STP) 互连

通过对串行输入数据流使用自适应输入均衡功能，可对

• 具有嵌入式时钟的直流均衡和扰频数据

传输介质损耗和确定性抖动进行补偿。通过使用低压

• 自适应电缆均衡

差分信令可最大限度减少电磁干扰 (EMI)。

• 图像增强（白平衡和抖动）和内部图案生成

• 汽车应用级产品：符合 AEC-Q100 2 级要求

器器件件信信息息

(1)

• >8kV 的人体模型 (HBM) 和 ISO 10605 静电放电

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

(ESD) 额定值

DS90UB928Q-Q1 WQFN (48) 7.00mm x 7.00mm

• 向后兼容模式

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

2 应应用用范范围围

• 汽车导航显示屏

• 后座娱乐系统

• 汽车驾驶员辅助系统

• 车载百万象素级摄像机系统

4 应应用用图图

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNLS417

DS90UB928Q-Q1

ZHCSDB5B –MARCH 2013–REVISED JANUARY 2015

www.ti.com.cn

目目录录

8.2 Functional Block Diagram ....................................... 16

1 特特性性.......................................................................... 1

8.3 Feature Description................................................. 17

2 应应用用范范围围................................................................... 1

8.4 Device Functional Modes........................................ 28

3 说说明明.......................................................................... 1

8.5 Programming........................................................... 36

4 应应用用图图 ...................................................................... 1

8.6 Register Maps......................................................... 37

5 修修订订历历史史记记录录 ........................................................... 2

9 Application and Implementation ........................ 53

6 Pin Configuration and Functions......................... 3

9.1 Application Information............................................ 53

7 Specifications......................................................... 5

9.2 Typical Application .................................................. 53

7.1 Absolute Maximum Ratings ..................................... 5

10 Power Supply Recommendations ..................... 56

7.2 ESD Ratings.............................................................. 6

11 Layout................................................................... 56

7.3 Recommended Operating Conditions....................... 6

11.1 Layout Guidelines ................................................. 56

7.4 Thermal Information.................................................. 6

11.2 Layout Example .................................................... 58

7.5 DC Electrical Characteristics .................................... 7

12 器器件件和和文文档档支支持持 ..................................................... 60

7.6 AC Electrical Characteristics..................................... 9

12.1 文档支持................................................................ 60

7.7 Timing Requirements for the Serial Control Bus .... 10

12.2 商标 ....................................................................... 60

7.8 Timing Requirements.............................................. 10

12.3 静电放电警告......................................................... 60

7.9 DC and AC Serial Control Bus Characteristics....... 11

12.4 术语表 ................................................................... 60

7.10 Typical Characteristics.......................................... 15

13 机机械械封封装装和和可可订订购购信信息息 .......................................... 60

8 Detailed Description............................................ 16

8.1 Overview ................................................................. 16

5 修修订订历历史史记记录录

Changes from Revision A (April 2013) to Revision B Page

• 已添加 ESD

额定值

表，

特性描述

部分，

器件功能模式

，

应用和实施

部分，

电源相关建议

部分，

布局

部分，

器件和文档

支持

部分以及

机械、封装和可订购信息

部分 ........................................................................................................................... 1

DS90UB928Q-Q1

ZHCSDB5B –MARCH 2013–REVISED JANUARY 2015

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NO.

GPIO_REG[8 8, 10, 7, 3 I/O, LVCMOS General Purpose I/O, register access only

:5] with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB

I2S_DA 7 O, LVCMOS Digital Audio Interface I2S Data Outputs

I2S_DB 3 Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3

I2S_DC 37

I2S_DD 36

INTB_IN 43 I, LVCMOS Interrupt Input

with pulldown Shared with BISTC

MCLK 11 O, LVCMOS Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs

I2S_WC 10 I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8

I2S_CLK 8

CONTROL AND CONFIGURATION

BISTC 43 I, LVCMOS BIST Clock Select

with pulldown Shared with INTB_IN

Requires a 10-kΩ pullup if set HIGH

BISTEN 9 I, LVCMOS BIST Enable

with pulldown Requires a 10-kΩ pullup if set HIGH

IDx 12 I, Analog I2C Address Select

External pullup to V

DD33

is required under all conditions. DO NOT FLOAT.

Connect to external pullup to V

DD33

and pulldown to GND to create a voltage divider.

See Table 6

LFMODE 32 I, LVCMOS Low Frequency Mode Select

with pulldown LFMODE = 0, 15 MHz ≤ TxCLKOUT ≤ 85 MHz (Default)

LFMODE = 1, 5 MHz ≤ TxCLKOUT < 15 MHz

Requires a 10-kΩ pullup if set HIGH

MAPSEL 26 I, LVCMOS FPD-Link Output Map Select

with pulldown MAPSEL = 0, LSBs on TxOUT3± (Default)

MAPSEL = 1, MSBs on TxOUT3±

Requires a 10-kΩ pullup if set HIGH

MODE_SEL 48 I, Analog Device Configuration Select

Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4-channel (I2S_B),

and Long Cable (LCBL) modes

Connect to external pullup to V

DD33

and pulldown to GND resistors to create a voltage

divider. DO NOT FLOAT

See Table 5

OEN 30 I, LVCMOS Output Enable

with pulldown Requires a 10-kΩ pullup if set HIGH

See Table 4

OSS_SEL 35 I, LVCMOS Output Sleep State Select

with pulldown Requires a 10-kΩ pullup if set HIGH

See Table 4

PDB 1 I, LVCMOS Power-down Mode Input Pin

Must be driven or pulled up to V

DD33

. Refer to “Power Up Requirements and PDB Pin" in the

Applications Information Section.

PDB = H, device is enabled (normal operation)

PDB = L, device is powered down

When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,

the PLL is shutdown, and I

is minimized. Control Registers are RESET.

SCL 5 I/O, Open I

C Clock Input/Output Interface

Drain Must have an external pullup to V

DD33

. DO NOT FLOAT

Recommended pullup: 4.7 kΩ

SDA 4 I/O, Open I2C Data Input/Output Interface

Drain Must have an external pullup to V

DD33

. DO NOT FLOAT

Recommended pullup: 4.7 kΩ

STATUS

LOCK 27 O, LVCMOS LOCK Status Output

0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states

controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.

1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL

Route to test point or pad (Recommended). Float if unused.

DS90UB928Q-Q1

www.ti.com.cn

ZHCSDB5B –MARCH 2013–REVISED JANUARY 2015

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NO.

PASS 28 O, LVCMOS PASS Status Output

0: One or more errors were detected in the received BIST payload (BIST Mode)

1: Error-free transmission (BIST Mode)

Route to test point or pad (Recommended). Float if unused.

FPD-LINK III SERIAL INTERFACE

CMF 42 Analog Common Mode Filter

Requires a 0.1-µF capacitor to GND

CMLOUTN 45 O, LVDS Inverting Loop-through Driver Output

Monitor point for equalized forward channel differential signal

CMLOUTP 44 O, LVDS True Loop-through Driver Output

Monitor point for equalized forward channel differential signal

RIN- 41 I/O, LVDS FPD-Link III Inverting Input

The output must be AC-coupled with a 0.1-µF capacitor

RIN+ 40 I/O, LVDS FPD-Link III True Input

The output must be AC-coupled with a 0.1-µF capacitor

POWER AND GROUND

(1)

GND DAP Ground Large metal contact at the bottom center of the device package

Connect to the ground plane (GND) with at least 9 vias

VDD33_A 38 Power 3.3-V Power to on-chip regulator

VDD33_B 31 Each pin requires a 4.7-µF capacitor to GND

VDDIO 6 Power 1.8 V/3.3 V LVCMOS I/O Power

Requires a 4.7-µF capacitor to GND

REGULATOR CAPACITOR

CAPI2S 2 CAP Decoupling capacitor connection for on-chip regulator

CAPLV25 25 Each requires a 4.7-µF decoupling capacitor to GND

CAPLV12 29

CAPR12 46

CAPP12 47

CAPL12 33 CAP Decoupling capacitor connection for on-chip regulator

Requires two 4.7-µF decoupling capacitors to GND

OTHER

RES[1:0] 39, 34 GND Reserved

Connect to GND

(1) The V

DD33

and V

DDIO

) supply ramp should be faster than 1.5 ms with a monotonic rise.

7 Specifications

7.1 Absolute Maximum Ratings

(1) (2)

MIN MAX UNIT

Supply Voltage – V

DD33

(3)

−0.3 4.0 V

Supply Voltage – V

DDIO

(3)

−0.3 4.0 V

LVCMOS I/O Voltage (V

DDIO

−0.3 V

0.3)

Deserializer Input Voltage −0.3 2.75 V

Junction Temperature 150 °C

48 LLP Package Maximum Power Dissipation Capacity at 25°C

Storage temperature, T

stg

−65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For soldering specifications, see product folder at www.ti.com and SNOA549.

(3) The DS90UB928Q-Q1V

DD33

and V

DDIO

voltages require a specific ramp rate during power up. The power supply ramp time must be less

than 1.5 ms with a monotonic rise.

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