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TI-DS90UB904Q-Q1.pdf
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FPD-Link解串器
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DS90UB903Q-Q1, DS90UB904Q-Q1
www.ti.com.cn
ZHCSB32E –JUNE 2010–REVISED APRIL 2013
具具有有双双向向控控制制通通道道的的 DS90UB903Q/DS90UB904Q 10 - 43MHz 18 位位彩彩色色
平平面面显显示示器器-链链路路 (FPD-Link) III 串串化化器器和和解解串串器器
查查询询样样品品: DS90UB903Q-Q1, DS90UB904Q-Q1
1
特特性性
说说明明
2
• 10MHz 至至 43MHz 输输入入并并行行端端口口时时钟钟 (PCLK) 支支持持
DS90UB903Q/DS90UB904Q 芯片组为一个单个差分
对上的数据传输提供了具有高速正向通道和一个双向控
• 210Mbps 至至 903Mbps 数数据据吞吞吐吐量量
制通道的 FPD-Link III 接口。 DS90UB903Q/904Q 在
• 单单个个差差分分对对互互连连
高速正向通道和双向控制通道数据路径上都包含差分信
• 具具有有 I
2
C 支支持持的的双双向向控控制制接接口口通通道道
令。 此串化器/解串器对针对图形主机控制器与显示模
• 具具有有 DC 平平衡衡编编码码的的嵌嵌入入式式时时钟钟以以支支持持 AC 耦耦合合互互
连连
块间的直接连接。 这个芯片组非常适合于将视频数据
• 能能够够驱驱动动长长达达 10 米米的的屏屏蔽蔽双双绞绞线线
驱动至要求 18 位色深(RGB666 + HS,VS 和 DE)
的显示屏以及双向控制通道总线。 主传输转换一个单
• I
2
C 兼兼容容串串行行接接口口
个高速串行数据流上的 21 位数据,连同一个从 I
2
C 端
• 单单个个硬硬件件器器件件寻寻址址引引脚脚
口上接受控制信息的独立低延迟双向控制通道传输。
• 多多达达 4 个个通通用用输输入入 (GPI) / 输输出出 (GPO)
使用德州仪器 (TI) 的嵌入时钟技术可实现一个单个差
• LOCK((锁锁定定))输输出出报报告告,,以以及及 AT-SPEED
BIST((全全速速内内置置自自检检))诊诊断断特特性性以以验验证证连连接接完完整整性性
分对上的透明全双工通信,从而在两个方向上携带非对
• 集集成成端端接接电电阻阻器器
称双向控制通道信息。 这个单个串行数据流通过消除
并行数据与时钟路径间的偏差,简化了印刷电路板
• 1.8V 或或 3.3V 兼兼容容并并行行数数据据接接口口
(PCB) 走线和电缆上的宽数据总线传输。 这样,通过
• 1.8V 单单电电源源
限制数据路径的宽度,大大节省了系统成本,相应地减
• 符符合合 ISO 10605 静静电电放放电电 (ESD) 以以及及 IEC 61000-
4-2 ESD 标标准准
少了 PCB 层数、电缆宽度以及连接器尺寸和引脚数
• 汽汽车车应应用用级级产产品品::符符合合 AEC-Q100 2 级级要要求求
量。
• 温温度度范范围围::-40°C 至至 +105°C
此外,解串器输入提供均衡控制来补偿较长距离介质所
• 解解串串器器上上无无需需基基准准时时钟钟
造成的损耗。 内部 DC 均衡编码/解码被用来支持 AC
• 可可编编程程接接收收均均衡衡
耦合互连。
• 电电磁磁干干扰扰 (EMI) / 电电磁磁兼兼容容性性 (EMC) 迁迁移移
此串化器采用 40 引脚超薄型四方扁平无引线 (WQFN)
– DES 可可编编程程展展频频 (SSCG) 输输出出
封装,而解串器采用 48 引脚 WQFN 封装。
– DES 接接收收器器交交错错输输出出
应应用用范范围围
• 汽汽车车显显示示系系统统
– 中中央央信信息息显显示示屏屏
– 导导航航显显示示屏屏
– 后后座座娱娱乐乐系系统统
– 触触控控显显示示屏屏
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not English Data Sheet: SNLS332
necessarily include testing of all parameters.

DS90UB904Q
Deserializer
Graphics
Controller
---
Video
Processor
DS90UB903Q
Serializer
PLL
Config.
I
2
C
PC
Config.
I
2
C
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PC
SDA
SCL
SDA
SCL
PCLK
FPD-Link III
PDB
MODE
GPO[3:0]
PDB
MODE
BISTEN
GPI[3:0]
Timing
Controller
LCD
Display
---
Touch Panel
R/G/B[5:0],
HS,VS,DE
21
DS90UB903Q - SERIALIZER
Clock
Gen
Timing
and
Control
DOUT-
RIN-
DS90UB904Q - DESERIALIZER
DOUT+
RIN+
Timing
and
Control
Input Latch
FIFO
Decoder
21
R/G/B[5:0],
HS,VS,DE
Encoder
Serializer
PLL
I2C Controller
Encoder
FIFO
Encoder
I2C Controller
Decoder
Deserializer
Decoder
Output Latch
Clock
Gen
CDR
R
T
R
T
R
T
R
T
LOCK
PCLK
SDA
SCL
GPI[3:0]
4
ID[x]
PASS
PCLK
SDA
SCL
GPO[3:0]
4
PDB
MODE
ID[x]
PDB
BISTEN
MODE
Display
Module,
Touch Panel
Deserializer
DS90UB903Q
Serializer
FPD-Link III
Bidirectional
Control Channel
DS90UB904Q
Bidirectional
Control Bus
Bidirectional
Control Bus
Parallel
Data In
Parallel
Data Out
18+3
2
2
Graphics
Controller
--
Video
Processor
18+3
GPO
GPI
4
4
DS90UB903Q-Q1, DS90UB904Q-Q1
ZHCSB32E –JUNE 2010–REVISED APRIL 2013
www.ti.com.cn
Typical Application Diagram
Figure 1. Typical Application Circuit
Block Diagrams
Figure 2. Block Diagram
Figure 3. Application Block Diagram
2 Copyright © 2010–2013, Texas Instruments Incorporated

11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
DS9UB903Q
Serializer
40-Pin WQFN
(Top View)
V
DDIO
DIN[8]
DIN[9]
V
DDD
DIN[10]
DIN[12]
DIN[13]
DIN[14]
DIN[15]
V
DDT
V
DDPLL
PDB
RES
MODE
DOUT-
GPO[1]
GPO[0]
V
DDCML
DOUT+
GPO[2]
GPO[3]
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
DIN[6]
DIN[7]
RES
ID[x]
SDA
SCL
DIN[20]
PCLK
DIN[19]
DIN[18]
DIN[17]
DIN[16]
DIN[11]
DAP = GND
DS90UB903Q-Q1, DS90UB904Q-Q1
www.ti.com.cn
ZHCSB32E –JUNE 2010–REVISED APRIL 2013
DS90UB903Q Pin Diagram
Serializer - DS90UB903Q
40 Pin WQFN (Top View)
See Package Number RTA0040A
DS90UB903Q SERIALIZER PIN DESCRIPTIONS
Pin Name Pin No. I/O, Type Description
LVCMOS PARALLEL INTERFACE
DIN[20:0] 5, 4, 3, 2, 1, Inputs, Parallel data inputs.
40, 39, 38, 37, LVCMOS
36, 35, 33, 32, w/ pull down
30, 29, 28, 27,
26, 25, 24, 23
PCLK 6 Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0] 22, 21, 20, 19 Output, General-purpose output pins can be used to control and respond to various
LVCMOS commands.
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 7
Open Drain SCL requires an external pull-up resistor to V
DDIO
.
Input/Output, Data line for the bidirectional control bus communication
SDA 8
Open Drain SDA requires an external pull-up resistor to V
DDIO
.
I
2
C Mode select
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Input, LVCMOS
MODE 12 Standby mode and is enabled through remote wakeup by Deserializer)
w/ pull down
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I
2
C
controller master on the bus. Slave mode does not generate the SCL clock, but uses
the clock generated by the Master for the data transfers.
Device ID Address Select
ID[x] 9 Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
Copyright © 2010–2013, Texas Instruments Incorporated 3

DS90UB903Q-Q1, DS90UB904Q-Q1
ZHCSB32E –JUNE 2010–REVISED APRIL 2013
www.ti.com.cn
DS90UB903Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name Pin No. I/O, Type Description
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB 13 PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
RES 10, 11
w/ pull down This pin MUST be tied LOW.
FPD-LINK III INTERFACE
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect
DOUT+ 17
CML must be AC Coupled with a 100 nF capacitor.
DOUT- 16 Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must
CML be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDPLL 14 Power, Analog PLL Power, 1.8V ±5%
VDDT 15 Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML 18 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD 34 Power, Digital Digital Power, 1.8V ±5%
Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V
DDIO
.
VDDIO 31
V
DDIO
can be connected to a 1.8V ±5% or 3.3V ±10%
Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS DAP the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
4 Copyright © 2010–2013, Texas Instruments Incorporated

DS90UB904Q
Deserializer
48-Pin WQFN
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
ROUT[14]
ROUT[15]
ROUT[17]
ROUT[18]
ROUT[20]
PCLK
SCL
SDA
ROUT[3]
ROUT[2]
ROUT[0]
V
DDIO1
GPI[1]
GPI[0]
PDB
V
DDR
V
DDSSCG
ROUT[19]
V
DDIO3
ROUT[16] ROUT[1]
GPI[3]
GPI[2]
LOCK
ROUT[13]
ROUT[11]
ROUT[6]
ROUT[4]
ROUT[12]
ROUT[5]
ROUT[10]
V
DDD
ROUT[9]
MODE
RES
V
DDPLL
BISTEN
RES
RIN-
RIN+
V
DDCML
RES/CMLOUTN
RES/CMLOUTP
ID[x]
PASS
ROUT[8]
ROUT[7]
V
DDIO2
DAP = GND
DS90UB903Q-Q1, DS90UB904Q-Q1
www.ti.com.cn
ZHCSB32E –JUNE 2010–REVISED APRIL 2013
DS90UB904Q Pin Diagram
Deserializer - DS90UB904Q
48 Pin WQFN (Top View)
See Package Number RHS0048A
DS90UB904Q DESERIALIZER PIN DESCRIPTIONS
Pin Name Pin No. I/O, Type Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0] 5, 6, 8, 9, 10, Outputs, Parallel data outputs.
11, 12, 13, 14, LVCMOS
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Output, Pixel Clock Output Pin.
PCLK 4
LVCMOS Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT (GPI)
General-purpose input pins can be used to control and respond to various
GPI[3:0] 30, 31, 32, 33 Input, LVCMOS
commands.
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 2
Open Drain SCL requires an external pull-up resistor to V
DDIO
.
Input/Output, Data line for bidirectional control bus communication
SDA 1
Open Drain SDA requires an external pull-up resistor to V
DDIO
.
I
2
C Mode select
MODE = L, Master mode; Device generates and drives the SCL clock line, where
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
MODE 47
w/ pull up MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an
I
2
C controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
Device ID Address Select
ID[x] 48 Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4.
CONTROL AND CONFIGURATION
Copyright © 2010–2013, Texas Instruments Incorporated 5
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