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FPD-Link串行器
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100Q STP Cable
FPD-Link Display Interface
RGB Display
720p
24-bit Color Depth
DS90UH927Q-Q1
Serializer
DS90UH928Q-Q1
Deserializer
FPD-Link III
1 Pair/AC Coupled
V
DDIO
(1.8V or 3.3V)
FPD-Link
FPD-Link
RxIN1+/-
RxCLKIN+/-
RxIN2+/-
RxIN0+/-
RxIN3+/-
TxOUT1+/-
TxCLKOUT+/-
TxOUT2+/-
TxOUT0+/-
TxOUT3+/-
V
DDIO
(1.8V or 3.3V)
HOST
Graphics
Processor
DOUT+
DOUT-
RIN+
RIN-
SDA
SCL
I2S
MCLK
6
6
V
DD33
(3.3V)
V
DD33
(3.3V)
MODE_SEL
BISTEN
LFMODE
MAPSEL
PDB
OSS_SEL
OEN
BKWD
REPEAT
LFMODE
MAPSEL
IDx
SDA
SCL
LOCK
PASS
PDB
INTB
I2S
INTB_IN
IDx
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
DS90UH927Q-Q1
ZHCSDA4C –NOVEMBER 2012–REVISED JANUARY 2015
DS90UH927Q-Q1 具具有有 HDCP 的的 5MHz 至至 85MHz 24 位位彩彩色色 FPD-Link III
串串行行器器
1 特特性性 3 说说明明
1
• 具有片上密钥存储器的集成型高带宽数字内容保护
DS90UH927Q-Q1 串行器与 DS90UH928Q-Q1 或
(HDCP) 加密引擎
DS90UH926Q-Q1 解串器配套使用,可针对汽车娱乐
• 双向控制通道接口,可连接到 I
2
C 兼容串行控制总
系统内的内容受保护数字视频的安全分发提供一套解决
线
方案。 该芯片组将 FPD-Link 视频接口转换为单对高
• 低电磁干扰 (EMI) FPD-Link 视频输入
速串行化接口。 数字视频数据采用业界标准的高带宽
• 支持高清 (720p) 数字视频格式
数字内容保护 (HDCP) 复制保护方案加以保护。 FPD-
• 支持 5MHz 至 85MHz 像素时钟 (PCLK)
Link III 串行总线方案支持通过单个差分链路实现高速
• 支持 RGB888 + VS、HS、DE 和 I
2
S 音频
正向通道数据传输和低速反向通道通信的全双工控制。
• 多达 4 个针对环绕立体声应用的 I
2
S 数字音频输入
通过单个差分对整合音频、视频和和控制数据可减小互
• 4 条具有 2 个专用引脚的双向通用输入输出 (GPIO)
连线尺寸和重量,同时还消除了偏差问题并简化了系统
通道
设计。
• 通过 1.8V 或 3.3V 兼容 LVCMOS I/O 接口实现
DS90UH927Q-Q1 串行器嵌入时钟,内容保护数据有
3.3V 单电源运行
效载荷,并将信号电平位移至高速差分信令。 多达 24
• 长达 10 米的交流耦合屏蔽双绞线 (STP) 互连
个 RGB 数据位连同 3 个视频控制信号和多达 4 个 I
2
S
• 具有嵌入式时钟的直流均衡和扰频数据
数据输入一起被串行化。
• 支持 HDCP 中继器应用
• 内部模式生成
凭借 FPD-Link 数据接口,该器件可轻松连接数据源,
• 低功率模式最大限度地减少了功率耗散
同时还能减小 EMI 和总线宽度。 通过使用低压差分信
• 汽车应用级产品:符合 AEC-Q100 2 级要求
令、数据扰频和随机生成以及直流均衡功能可最大程度
• >8kV 的人体模型 (HBM) 和 ISO 10605 静电放电
减少高速 FPD-Link III 总线上的 EMI。
(ESD) 额定值
串化器和解串器上都执行 HDCP 密钥引擎。 HDCP 密
• 向后兼容模式
钥被存储在片载存储器中。
2 应应用用范范围围
器器件件信信息息
(1)
• 汽车导航显示屏
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
• 后座娱乐系统
DS90UH927Q-Q1 WQFN (40) 6.00mm x 6.00mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
应应用用图图
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNLS433
DS90UH927Q-Q1
ZHCSDA4C –NOVEMBER 2012–REVISED JANUARY 2015
www.ti.com.cn
目目录录
7.2 Functional Block Diagram ....................................... 15
1 特特性性.......................................................................... 1
7.3 Feature Description................................................. 16
2 应应用用范范围围................................................................... 1
7.4 Device Functional Modes........................................ 24
3 说说明明.......................................................................... 1
7.5 Programming........................................................... 30
4 修修订订历历史史记记录录 ........................................................... 2
7.6 Register Maps......................................................... 32
5 Pin Configuration and Functions......................... 3
8 Application and Implementation ........................ 52
6 Specifications......................................................... 5
8.1 Application Information............................................ 52
6.1 Absolute Maximum Ratings ...................................... 5
8.2 Typical Application .................................................. 52
6.2 ESD Ratings.............................................................. 5
9 Power Supply Recommendations...................... 54
6.3 Recommended Operating Conditions....................... 6
10 Layout................................................................... 55
6.4 Thermal Information.................................................. 6
10.1 Layout Guidelines ................................................. 55
6.5 DC Electrical Characteristics .................................... 7
10.2 Layout Example .................................................... 56
6.6 AC Electrical Characteristics..................................... 9
11 器器件件和和文文档档支支持持 ..................................................... 60
6.7 DC and AC Serial Control Bus Characteristics....... 10
11.1 文档支持................................................................ 60
6.8 Recommended Timing Requirements for the Serial
Control Bus .............................................................. 10
11.2 商标 ....................................................................... 60
6.9 Timing Requirements.............................................. 11
11.3 静电放电警告......................................................... 60
6.10 Typical Characteristics.......................................... 14
11.4 术语表 ................................................................... 60
7 Detailed Description............................................ 15
12 机机械械封封装装和和可可订订购购信信息息 .......................................... 60
7.1 Overview ................................................................. 15
4 修修订订历历史史记记录录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2013) to Revision C Page
• 已添加 ESD
额定值
表,
特性描述
部分,
器件功能模式
,
应用和实施
部分,
电源相关建议
部分,
布局
部分,
器件和文档
支持
部分以及
机械、封装和可订购信息
部分 ........................................................................................................................... 1
Changes from Revision A (November 2012) to Revision B Page
• Changed layout of National data sheet to TI format............................................................................................................. 56
2 Copyright © 2012–2015, Texas Instruments Incorporated
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
RxIN1-
RxIN1+
RxIN2-
RxIN2+
RxCLKIN-
GPIO1
RxIN3-
RxIN3+
GPIO0
RES1
CAPHS12
RES0
IDx
CAPP12
DOUT-
CMF
VDD33_A
PDB
DOUT+
REPEAT
BKWD
MAPSEL
LFMODE
VDD33_B
I2S_WC/GPIO_REG7
CAPLVD12
RxIN0-
RxIN0+
SDA
SCL
CAPL12
VDDIO
I2S_DC/GPI02
I2S_DD/GPI03
I2S_DB/GPIO_REG5
I2S_DA/GPIO_REG6
I2S_CLK/GPIO_REG8
INTB
RxCLKIN+
VDDIO
30
29
28
27
26
25
24
23
22
21
DS90UH927Q-Q1
TOP VIEW
DAP = GND
10
DS90UH927Q-Q1
www.ti.com.cn
ZHCSDA4C –NOVEMBER 2012–REVISED JANUARY 2015
5 Pin Configuration and Functions
RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
Pin Functions
PIN
I/O, TYPE DESCRIPTION
NAME NO.
FPD-LINK INPUT INTERFACE
RxCLKIN- 35 I, LVDS Inverting LVDS Clock Input
The pair requires external 100-Ω differential termination for standard LVDS levels
RxCLKIN+ 36 I, LVDS True LVDS Clock Input
The pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]- 37, 33, 31, 29 I, LVDS Inverting LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]+ 38, 34, 32, 30 I, LVDS True LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
LVCMOS PARALLEL INTERFACE
BKWD 22 I, LVCMOS Backward Compatible Mode Select
w/ pull down BKWD = 0, interfacing to DS90UH926/8Q-Q1 (Default)
BKWD = 1, interfacing to DS90UR906/8Q-Q1, DS90UR916Q
Requires a 10-kΩ pullup if set HIGH
GPIO[1:0] 40, 39 I/O, LVCMOS General Purpose I/O
w/ pull down See Table 1
Copyright © 2012–2015, Texas Instruments Incorporated 3
DS90UH927Q-Q1
ZHCSDA4C –NOVEMBER 2012–REVISED JANUARY 2015
www.ti.com.cn
Pin Functions (continued)
PIN
I/O, TYPE DESCRIPTION
NAME NO.
I2S_DA 3 I, LVCMOS Digital Audio Interface I
2
S Data Inputs
I2S_DB 4 w/ pull down Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
I2S_DC 5
I2S_DD 6
I2S_WC 1 I, LVCMOS Digital Audio Interface I
2
S Word Clock and I
2
S Bit Clock Inputs
I2S_CLK 2 w/ pull down Shared with GPIO_REG7 and GPIO_REG8
Table 3
LFMODE 25 I, LVCMOS Low Frequency Mode Select
w/ pull down LFMODE = 0, 15 MHz ≤ RxCLKIN ≤ 85 MHz (Default)
LFMODE = 1, 5 MHz ≤ RxCLKIN < 15 MHz
Requires a 10-kΩ pullup if set HIGH
MAPSEL 23 I, LVCMOS FPD-Link Input Map Select
w/ pull down MAPSEL = 0, LSBs on RxIN3± (Default)
MAPSEL = 1, MSBs on RxIN3±
See Figure 19 and Figure 20
Requires a 10-kΩ pullup if set HIGH
REPEAT 21 I, LVCMOS Repeater Mode Select
w/ pull down REPEAT = 0, Repeater Mode disabled (Default)
REPEAT = 1, Repeater Mode enabled
Requires a 10-kΩ pullup if set HIGH
OPTIONAL PARALLEL INTERFACE
GPIO[3:2] 6, 5 I/O, LVCMOS General Purpose I/O
w/ pull down Shared with I2S_DD and I2S_DC
See Table 1
GPIO_REG[ 2, 1, 3, 4 I/O, LVCMOS Register-Only General Purpose I/O
8:5] w/ pull down Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
See Table 2
CONTROL AND CONFIGURATION
IDx 11 I, Analog I
2
C Address Select
External pullup to V
DD33
is required under all conditions. DO NOT FLOAT.
Connect to external pullup to V
DD33
and pulldown to GND to create a voltage divider.
See Figure 25 and Table 4
PDB 18 I, LVCMOS Power-down Mode Input Pin
w/ pulldown Must be driven or pulled up to V
DD33
. Refer to Power Supply Recommendations.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and I
DD
is minimized. Control Registers are RESET.
SCL 9 I/O, LVCMOS I
2
C Clock Input / Output Interface
Open Drain Must have an external pullup to V
DD33
. DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
SDA 10 I/O, LVCMOS I
2
C Data Input / Output Interface
Open Drain Must have an external pullup to V
DD33
. DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
STATUS
INTB 27 O, LVCMOS HDCP Interrupt
Open Drain INTB = H, normal
INTB = L, Interrupt request
Recommended pullup: 4.7 kΩ to V
DDIO
. DO NOT FLOAT.
FPD-LINK III SERIAL INTERFACE
CMF 20 Analog Common Mode Filter.
Connect 0.1 µF to GND (required)
DOUT- 16 I/O, LVDS Inverting Output
The output must be AC-coupled with a 0.1-µF capacitor.
DOUT+ 17 I/O, LVDS True Output
The output must be AC-coupled with a 0.1-µF capacitor.
4 Copyright © 2012–2015, Texas Instruments Incorporated
DS90UH927Q-Q1
www.ti.com.cn
ZHCSDA4C –NOVEMBER 2012–REVISED JANUARY 2015
Pin Functions (continued)
PIN
I/O, TYPE DESCRIPTION
NAME NO.
POWER AND GROUND
(1)
GND DAP Ground Large metal contact at the bottom center of the device package Connect to the ground
plane (GND) with at least 9 vias.
VDD33_A 19 Power Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7 µF capacitor to GND
VDD33_B 26
VDDIO 7, 24 Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7 µF capacitor to GND
REGULATOR CAPACITOR
CAPP12 12 CAP Decoupling capacitor connection for on-chip regulator
CAPHS12 14 Each requires a 4.7-µF decoupling capacitor to GND.
CAPLVD12 28
CAPL12 8 CAP Decoupling capacitor connection for on-chip regulator
Requires two 4.7-µF decoupling capacitors to GND
OTHER
RES[1:0] 15, 13 GND Reserved
Connect to GND.
(1) The V
DD
(V
DD33
and V
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise.
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)(3)
MIN MAX UNIT
Supply Voltage – V
DD33
(4)
−0.3 4.0 V
Supply Voltage – V
DDIO
(4)
−0.3 4.0 V
LVCMOS I/O Voltage (V
DDIO
+
−0.3 0.3) V
Serializer Output Voltage −0.3 2.75 V
Junction Temperature 150 °C
Storage Temperature, T
stg
−65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) The DS90UH927Q-Q1 V
DD33
and V
DDIO
voltages require a specific ramp rate during power up. The power supply ramp time must be
less than 1.5 ms with a monotonic rise
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002
(1)
±8000
Charged device model (CDM), per AEC Q100-011 ±1250 V
Machine model (MM) ±250
(IEC 61000-4-2, powered-up only) Air Discharge
R
D
= 330 Ω, C
S
= 150 pF (Pin 16 and 17) ±15000
Electrostatic
V
(ESD)
Contact Discharge
discharge
(Pin 16 and 17) ±8000
V
(ISO 10605) Air Discharge
R
D
= 330 Ω, C
S
= 150 pF/330 pF (Pin 16 and 17) ±15000
R
D
= 2 kΩ, C
S
= 150 pF/330 pF
Contact Discharge
(Pin 16 and 17) ±8000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Copyright © 2012–2015, Texas Instruments Incorporated 5
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