没有合适的资源?快使用搜索试试~ 我知道了~
TI-DS90UB913Q-Q1.pdf
需积分: 0 14 浏览量
2023-02-01
22:56:03
上传
评论 4
收藏 1.68MB PDF 举报
温馨提示
FPD-Link串行器
资源推荐
资源详情
资源评论


DSP, FPGA/
µ-Processor/
ECU
Deserializer
DS90UB913Q
Serializer
FPD-Link III
Bidirectional
Control Channel
DS90UB914Q
Bidirectional
Control Bus
Bidirectional
Control Bus
Parallel
Data In
Parallel
Data Out
10 or 12
2
2
Megapixel
Imager/Sensor
10 or 12
GPO
GPIO
4
4
2
HSYNC,
VSYNC
2
HSYNC,
VSYNC
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
DS90UB913Q-Q1
,
DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
DS90UB91xQ-Q1 具具有有双双向向控控制制通通道道的的 10MHz 至至 100MHz、、10 位位和和 12
位位直直流流均均衡衡 FPD-Link III 串串行行器器和和解解串串器器
1 特特性性 – 接收器交错输出
1
• 10MHz 至 100MHz 输入像素时钟支持
2 应应用用
• 单个差分对互连
• 前置摄像头或后置摄像头,实现碰撞缓解
• 可编程的数据有效载荷:
• 停车辅助系统环视
– 10 位有效载荷,高达 100MHz
– 12 位有效载荷,高达 75MHz
3 说说明明
• 连续低延迟双向控制接口通道,支持 I
2
C,频率达
DS90UB91xQ-Q1 芯片组提供一个具有高速正向通道
400kHz
和双向控制通道的 FPD-Link III 接口,用来实现单一差
• 2:1 多路复用器,可在两个输入成像器之间进行选
分对上的数据传输。 DS90UB91xQ-Q1 芯片组的高速
择
正向通道和双向控制通道数据路径上均包含差分信令。
• 具有直流均衡编码的嵌入式时钟,支持交流耦合互
串行器和解串器对主要用于电子控制单元 (ECU) 中成
连
像器与视频处理器的连接。 该芯片组非常适用于驱动
• 能够驱动长达 25 米的屏蔽双绞线
需要高达 12 位像素深度、2 个同步信号以及双向控制
• 接收均衡器自动适应电缆损耗的变化
通道总线的视频数据。
• 串行器和解串器上均提供有 4 个专用通用输入/输出
引脚 (GPIO)
解串器上有一个多路复用器,可用于在两个输入成像器
• LOCK 输出报告引脚和 AT-SPEED BIST (全速内
之间进行选择。 解串器只能激活一个输入成像器。 主
置自检)诊断特性,可验证链路完整性
视频传输将 10 位和 12 位数据转换为单条高速串行数
• 串行器上提供 1.8V、2.8V 或 3.3V 兼容并行输入
据流,另外一个独立的低延迟双向控制通道传输负责接
• 1.8V 单电源
收来自 I
2
C 端口的控制信息,与视频消隐期无关。
• 符合 ISO 10605 和 IEC 61000-4-2 静电放电
(ESD) 标准
器器件件信信息息
(1)
• 汽车级产品:符合 AEC-Q100 2 级要求
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
• 温度范围:-40°C 至 +105°C
DS90UB913Q-Q1 WQFN (32) 5.00mm x 5.00mm
DS90UB914Q-Q1 WQFN (48) 7.00mm x 7.00mm
• 小尺寸串行器 (5mm × 5mm)
• 解串器上提供 EMI/EMC 缓解功能
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
– 可编程扩频 (SSCG) 输出
典典型型应应用用电电路路
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNLS420

DS90UB913Q-Q1
,
DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
目目录录
9.1 AC Timing Diagrams and Test Circuits................... 20
1 特特性性.......................................................................... 1
10 Detailed Description ........................................... 25
2 应应用用.......................................................................... 1
10.1 Overview ............................................................... 25
3 说说明明.......................................................................... 1
10.2 Functional Block Diagram ..................................... 25
4 修修订订历历史史记记录录 ........................................................... 2
10.3 Feature Description............................................... 26
5 说说明明((续续))............................................................... 3
10.4 Device Functional Modes...................................... 33
6 器器件件比比较较表表............................................................... 3
10.5 Register Maps....................................................... 41
7 Pin Configuration and Functions......................... 4
11 Application and Implementation........................ 56
8 Specifications......................................................... 9
11.1 Applications Information........................................ 56
8.1 Absolute Maximum Ratings ...................................... 9
11.2 Typical Application ................................................ 56
8.2 ESD Ratings.............................................................. 9
12 Power Supply Recommendations ..................... 60
8.3 Recommended Operating Conditions....................... 9
13 Layout................................................................... 60
8.4 Thermal Information................................................ 10
13.1 Layout Guidelines ................................................. 60
8.5 Electrical Characteristics ........................................ 10
13.2 Layout Example .................................................... 61
8.6 Timing Requirements: Recommended for Serializer
14 器器件件和和文文档档支支持持 ..................................................... 63
PCLK ....................................................................... 14
14.1 文档支持 ............................................................... 63
8.7 AC Timing Specifications (SCL, SDA) - I
2
C
Compliant................................................................. 15
14.2 相关链接................................................................ 63
8.8 Bidirectional Control Bus DC Timing Specifications
14.3 社区资源................................................................ 63
(SCL, SDA) - I
2
C Compliant..................................... 15
14.4 商标 ....................................................................... 63
8.9 Switching Characteristics: Serializer....................... 16
14.5 静电放电警告......................................................... 63
8.10 Switching Characteristics: Deserializer................. 17
14.6 Glossary................................................................ 63
8.11 Typical Characteristics.......................................... 19
15 机机械械、、封封装装和和可可订订购购信信息息....................................... 63
9 Parameter Measurement Information ................ 20
4 修修订订历历史史记记录录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2014) to Revision D Page
• 已添加
引脚配置和功能
部分,ESD
额定值
表,
特性描述
部分,
器件功能模式
,
应用和实施
部分,
电源相关建议
部分,
布局
部分,
器件和文档支持
部分以及
机械、封装和可订购信息
部分........................................................................................ 1
• 已更新数据表以符合新的 TI 布局............................................................................................................................................ 1
• Added text and graphic to Power Up Requirements ........................................................................................................... 39
Changes from Revision B (April 2013) to Revision C Page
• Changed "PCLK from imager mode" value in DS90UB913Q Serializer MODE Resistor Value table from 0 kΩ to 100
kΩ ......................................................................................................................................................................................... 35
• Changed Falling to Rising in RRFB...................................................................................................................................... 47
• Changed Rising to Falling in RRFB...................................................................................................................................... 47
Changes from Revision A (April 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 61
2 版权 © 2012–2015, Texas Instruments Incorporated

DS90UB913Q-Q1
,
DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
5 说说明明((续续))
凭借德州仪器 (TI) 的嵌入式时钟技术,可在单一差分对上进行透明的全双工通信,两个方向上运载不对称的双向控
制通道信息。 这种单一串行数据流通过消除并行数据与时钟路径间的偏差,简化了印刷电路板 (PCB) 走线和电缆
上的宽数据总线传输。 这样,通过限制路径的宽度,大大节省了系统成本,相应地减少了 PCB 层数、电缆宽度以
及连接器尺寸和引脚数量。 此外,解串器输入还提供自适应均衡功能来补偿较长距离介质上的损耗。 内部直流均
衡编码和解码被用来支持交流耦合互连。 此串化器采用 32 引脚超薄型四方扁平无引线 (WQFN) 封装,而解串器采
用 48 引脚 WQFN 封装。
6 器器件件比比较较表表
器器件件编编号号 FPD-III 功功能能 封封装装 传传输输介介质质 PCLK 频频率率
DS90UB913Q-Q1 串行器 32 引脚 RTV (WQFN) STP 10MHz 至 100MHz
DS90UB913A-Q1 串行器 32 引脚 RTV (WQFN) 同轴或屏蔽双绞线 (STP) 25MHz 至 100MHz
DS90UB914Q-Q1 解串器 48 引脚 RHS (WQFN) STP 10MHz 至 100MHz
DS90UB914A-Q1 解串器 48 引脚 RHS (WQFN) 同轴或 STP 25MHz 至 100MHz
Copyright © 2012–2015, Texas Instruments Incorporated 3

32 31 30 29 28 27 26
25
1 2 3 4 5 6 7
8
9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
DS90UB913Q
Serializer
VDDIO
DIN[8]
DIN[9]
DIN[10]
DIN[11]
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
VDDCML
VDDT
VDDPLL
PDB
DOUT-
DOUT+
HSYNC
VSYNC
PCLK
SCL
SDA
ID[x]
RES
MODE
GPO[2]/
CLKOUT
GPO[1]
GPO[0]
VDDD
GPO[3]/
CLKIN
DAP = GND
DS90UB913Q-Q1
,
DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
7 Pin Configuration and Functions
RTV Package
32-Pin WQFN
Top View
DS90UB913Q-Q1 Serializer Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
19, 20, 21,
Inputs,
22, 23, 24,
DIN[0:11] LVCMOS Parallel data inputs
26, 27, 29,
with pulldown
30, 31, 32
Inputs,
HSYNC 1 LVCMOS Horizontal SYNC input
with pulldown
Input, LVCMOS Pixel clock input pin
PCLK 3
with pulldown Strobe edge set by TRFB control register.
Inputs,
VSYNC 2 LVCMOS Vertical SYNC input
with pulldown
4 Copyright © 2012–2015, Texas Instruments Incorporated

DS90UB913Q-Q1
,
DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
DS90UB913Q-Q1 Serializer Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
GENERAL-PURPOSE OUTPUT (GPO)
General-purpose output pins can be configured as outputs; used to control and respond
Output, to various commands. GPO[0:1] can be configured to be the outputs for input signals
GPO[1:0] 16, 15
LVCMOS coming from GPIO[0:1] pins on the deserializer or can be configured to be outputs of
the local register on the serializer.
GPO2 pin can be configured to be the output for input signal coming from the GPIO2
pin on the deserializer or can be configured to be the output of the local register on the
GPO[2]/ Output, serializer. It can also be configured to be the output clock pin when the DS90UB913Q-
17
CLKOUT LVCMOS Q1 device is used in the External Oscillator mode. See Applications Information for a
detailed description of the DS90UB91xQ-Q1 chipsets working with the external
oscillator.
GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
on the deserializer or can be configured to be the output of the local register setting on
GPO[3]/ Input/Output, the serializer. It can also be configured to be the input clock pin when the
18
CLKIN LVCMOS DS90UB913Q-Q1 serializer is working with an external oscillator. See Applications
Information section for a detailed description of the DS90UB91xQ-Q1 chipsets working
with an external oscillator.
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 4
Open-Drain SCL requires an external pullup resistor to V
DDIO
.
Input/Output, Data line for the bidirectional control bus communication
SDA 5
Open-Drain SDA requires an external pullup resistor to V
DDIO
.
Device mode select
Input, LVCMOS Resistor to Ground and 10-kΩ pullup to 1.8-V rail. MODE pin on the serializer can be
MODE 8
with pulldown used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in Table 3.
Device ID address select
ID[x] 6 Input, analog The ID[x] pin on the serializer is used to assign the I
2
C device address. Resistor to
Ground and 10-kΩ pullup to 1.8-V rail. See Table 1.
CONTROL AND CONFIGURATION
Power down Mode Input Pin
PDB = H, serializer is enabled and is ON.
Input, LVCMOS
PDB 9 PDB = L, Serailizer is in power-down mode. When the serializer is in power-down, the
with pulldown
PLL is shutdown, and IDD is minimized. Programmed control register data are NOT
retained and reset to default values
Input, LVCMOS Reserved
RES 7
with pulldown This pin MUST be tied LOW.
FPD-Link III INTERFACE
Input/Output, Noninverting differential output, bidirectional control channel input. The interconnect
DOUT+ 13
CML must be AC-coupled with a 100-nF capacitor.
Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must be
DOUT– 12
CML AC-coupled with a 100-nF capacitor.
POWER AND GROUND
VDDPLL 10 Power, Analog PLL Power, 1.8 V ±5%
VDDT 11 Power, Analog Tx Analog Power, 1.8 V ±5%
VDDCML 14 Power, Analog CML and bidirectional channel driver power, 1.8 V ±5%
VDDD 28 Power, Digital Digital power, 1.8 V ±5%
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V
DDIO
.
VDDIO 25 Power, Digital
V
DDIO
can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS DAP Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least 9
vias.
Copyright © 2012–2015, Texas Instruments Incorporated 5
剩余71页未读,继续阅读
资源评论


不觉明了
- 粉丝: 834
- 资源: 4209
上传资源 快速赚钱
我的内容管理 收起
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助


会员权益专享
安全验证
文档复制为VIP权益,开通VIP直接复制
