TI-DS90UH949A-Q1.pdf

DS90UH949A-Q1 VQFN (64) 9.00mm x 9.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

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6.1 Absolute Maximum Ratings ..................................... 7

6.2 ESD Ratings ............................................................ 7

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 8

6.5 DC Electrical Characteristics .................................... 8

6.6 AC Electrical Characteristics..................................... 9

6.7 DC and AC Serial Control Bus Characteristics....... 11

6.8 Recommended Timing for the Serial Control Bus .. 11

IN_D1+

60

IN_D2-

IN_D2+

62

63

I, TMDS TMDS Data Channel 2 Differential Input

HPD 42 O, Open-

Drain

Hot Plug Detect Output. Pull up to RX_5V with a 1-kΩ resistor

RX_5V 43 I HDMI 5-V Detect Input

DDC_SDA 44 IO, Open-

Drain

DDC Slave Serial Data

Pull up to RX_5V with a 47-kΩ resistor

4

Drain

Pullup with a 27-kΩ resistor to 3.3 V

X1 39 I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be

connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level

1.8 V. Leave it open if unused.

DOUT0- 26 O FPD-Link III Inverting Output 0

The output must be AC-coupled with a 0.1-μF capacitor for interfacing with 92x deserializers

and 0.1-μF or 33-nF capacitor for 94x deserializers

DOUT0+ 27 O FPD-Link III True Output 0

The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers

LFT 20 Analog FPD-Link III Loop Filter

Connect to a 10-nF capacitor to GND

SDA 14 IO, Open-

Drain

I2C Data Input / Output Interface

Open-drain. Must have an external pullup to resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO

Recommended pullup: 4.7 kΩ.

SCL 15 IO, Open-

Drain

I2C Clock Input / Output Interface

Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO

IDx 19 Analog I2C Serial Control Bus Device ID Address Select

MODE_SEL0 18 Analog Mode Select 0. See 表 6.

MODE_SEL1 32 Analog Mode Select 1. See 表 6.

PDB 31 I, LVCMOS Power-Down Mode Input Pin

INTB 13 O, Open-

Drain

Open-Drain. Remote interrupt. Active LOW.

Pull up to VDDIO with a 4.7-kΩ resistor.

REM_INTB 40 O, Open-

Drain

Remote interrupt. Mirrors status of INTB_IN from the deserializer.

Note: External pull-up to 1.8 V required. Recommended pullup: 4.7 kΩ.

INTB = H, Normal Operation

INTB = L, Interrupt Request

D_GPIO0 8 IO, LVCMOS HS GPIO0. Shared with MOSI

D_GPIO1 10 IO, LVCMOS HS GPIO1. Shared with MISO

GPIO0 4 IO, LVCMOS BCC GPIO0. Shared with SDIN

GPIO1 5 IO, LVCMOS BCC GPIO1. Shared with SWC

GPIO2 37 IO, LVCMOS BCC GPIO2. Shared with I2S_DC

GPIO3 38 IO, LVCMOS BCC GPIO3. Shared with I2S_DD

GPIO5_REG 36 IO, LVCMOS General-Purpose Input/Output 5

Local register control only. Shared with I2S_DB

GPIO6_REG 35 IO, LVCMOS General-Purpose Input/Output 6

Local register control only. Shared with I2S_DA

I2S_CLK 34 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG

I2S_DA 35 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG

I2S_DB 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG

I2S_DC 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2

I2S_DD 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3

SWC 5 O, LVCMOS Master Mode I2S Word Clock Ouput. Shared with GPIO1

SCLK 6 O, LVCMOS Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up

as I2CSEL, then it will switch to SCLK operation as an output.

SDIN 4 I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0

51

64

VDDA11 9 Power 1.1-V (±5%) Analog supply. Refer to 图 25 or 图 26.

VDDHA11 52

54

58

61

Power 1.1-V (±5%) TMDS supply. Refer to 图 25 or 图 26.

VDDHS11 21

28

Power 1.1-V (±5%) supply. Refer to 图 25 or 图 26.

VDDL11 7

Power 1.1-V (±5%) Digital supply. Refer to 图 25 or 图 26.

Pad