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FPD-Link III

2 Lane

VDDIO

1.8V

IDx

DOUT0+

DOUT0-

1.1V

IN_CLK-/+

HDMI

HPD

DDC

CEC

DOUT1+

DOUT1-

RIN0+

RIN0-

RIN1+

RIN1-

CLK+/-

CLK2+/-

FPD-Link

(Open LDI)

D0+/-

D1+/-

D2+/-

D3+/-

D4+/-

D5+/-

D6+/-

D7+/-

DS90UB949-Q1

Serializer

DS90UB948-Q1

Deserializer

IDx

D_GPIO

(SPI)

D_GPIO

(SPI)

LVDS

Display

1080p60

or Graphic

Processor

Graphics

Processor

IN_D0-/+

IN_D1-/+

IN_D2-/+

I2C

VDDIO

(3.3V / 1.8V)

3.3V

I2C

1.2V1.8V

HDMI ± High Definition Multimedia Interface

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

DS90UB949-Q1 1080p HDMI to FPD-Link III Bridge Serializer

1 Features 3 Description

The DS90UB949-Q1 is a HDMI to FPD-Link III bridge

• Supports TMDS Clock up to 170 MHz for WUXGA

device which, in conjunction with the FPD-Link III

(1920x1200) and 1080p60 Resolutions with 24-Bit

DS90UB940-Q1/DS90UB948-Q1 deserializers,

Color Depth

provides 1-lane or 2-lane high-speed serial streams

• Single and Dual FPD-Link III Outputs

over cost-effective 50Ω single-ended coaxial or 100Ω

differential shielded twisted-pair (STP) cables. It

• High-Definition Multimedia (HDMI) v1.4b Inputs

serializes a HDMI v1.4b input supporting video

• HDMI-Mode DisplayPort (DP++) Inputs

resolutions up to WUXGA and 1080p60 with 24-bit

• HDMI Audio Extraction for up to 8 Channels

color depth.

• High Speed Back Channel Supporting GPIO up to

The FPD-Link III interface supports video and audio

2 Mbps

data transmission and full duplex control, including

• Supports up to 15 Meters of Cable with Automatic

I2C and SPI communication, over the same

Temperature and Aging Compensation

differential link. Consolidation of video data and

control over two differential pairs reduces the

• Tracks Spread Spectrum Input Clock to Reduce

interconnect size and weight and simplifies system

EMI

design. EMI is minimized by the use of low voltage

• I2C (Master/Slave) with 1Mbps Fast-Mode Plus

differential signaling, data scrambling, and

• SPI Pass-Through Interface

randomization. In backward compatible mode, the

device supports up to WXGA and 720p resolutions

• Backward compatible with DS90UB926Q-Q1 and

with 24-bit color depth over a single differential link.

DS90UB928Q-Q1 FPD-Link III Deserializers

• Automotive Grade Product: AEC-Q100 Grade 2

The DS90UB949-Q1 supports multi-channel audio

received through HDMI or an external I2S interface.

Qualified

The device also supports an optional auxiliary audio

interface.

2 Applications

• Automotive Infotainment:

Device Information(1)

– IVI Head Units and HMI Modules

PART NUMBER PACKAGE BODY SIZE (NOM)

– Rear Seat Entertainment Systems

DS90UB949-Q1 VQFN RGC (64) 9.00 mm X 9.00 mm

– Digital Instrument Clusters

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

• Security and Surveillance Camera

• Consumer Input HDMI Port

4 Applications Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

www.ti.com

Table of Contents

8.3 Feature Description................................................. 18

1 Features.................................................................. 1

8.4 Device Functional Modes........................................ 31

2 Applications ........................................................... 1

8.5 Programming........................................................... 33

3 Description ............................................................. 1

8.6 Register Maps......................................................... 37

4 Applications Diagram............................................ 1

9 Application and Implementation ........................ 66

5 Revision History..................................................... 2

9.1 Applications Information.......................................... 66

6 Pin Configuration and Functions......................... 3

9.2 Typical Applications ................................................ 66

7 Specifications......................................................... 7

10 Power Supply Recommendations ..................... 71

7.1 Absolute Maximum Ratings ..................................... 7

10.1 Power Up Requirements And PDB Pin................. 71

7.2 Handling Ratings....................................................... 7

11 Layout................................................................... 72

7.3 Recommended Operating Conditions....................... 7

11.1 Layout Guidelines ................................................. 72

7.4 Thermal Information.................................................. 8

11.2 Layout Example .................................................... 73

7.5 DC Electrical Characteristics .................................... 9

12 Device and Documentation Support ................. 74

7.6 AC Electrical Characteristics................................... 11

12.1 Documentation Support ....................................... 74

7.7 DC And AC Serial Control Bus Characteristics ...... 12

12.2 Trademarks........................................................... 74

7.8 Recommended Timing for the Serial Control Bus .. 13

12.3 Electrostatic Discharge Caution............................ 74

7.9 Typical Characteristics............................................ 16

12.4 Glossary................................................................ 74

8 Detailed Description............................................ 17

13 Mechanical, Packaging and Orderable

8.1 Overview ................................................................. 17

Information ........................................................... 74

8.2 Functional Block Diagram ....................................... 17

5 Revision History

DATE REVISION NOTES

November 2014 * Initial release.

Product Folder Links: DS90UB949-Q1

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

www.ti.com

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NO.

CEC 1 IO, Open- Consumer Electronic Control Channel Input/Output Interface.

Drain Pull-up with a 27kΩ resistor to 3.3V

X1 39 I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be

connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level

1.8V. Leave it open if unused.

FPD-LINK III SERIAL

DOUT0- 26 O FPD-Link III Inverting Output 0

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

DOUT0+ 27 O FPD-Link III True Output 0

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

DOUT1- 22 O FPD-Link III Inverting Output 1

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

DOUT1+ 23 O FPD-Link III True Output 1

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

LFT 20 Analog FPD-Link III Loop Filter

Connect to a 10nF capacitor to GND

CONTROL

SDA 14 IO, Open- I2C Data Input / Output Interface

Drain Open drain. Must have an external pull-up to resistor to 1.8V or 3.3V. See I2CSEL pin. DO

NOT FLOAT.

Recommended pull-up: 4.7kΩ.

SCL 15 IO, Open- I2C Clock Input / Output Interface

Drain Open drain. Must have an external pull-up resistor to 1.8V or 3.3V. See I2CSEL pin. DO

NOT FLOAT.

Recommended pull-up: 4.7kΩ.

I2CSEL 6 I, LVCMOS I2C Voltage Level Strap Option

Tie to V

DDIO

with a 10kΩ resistor for 1.8V I2C operation.

Leave floating for 3.3V I2C operation.

This pin is read as an input at power up.

IDx 19 Analog I2C Serial Control Bus Device ID Address Select

MODE_SEL0 18 Analog Mode Select 0. See Table 6.

MODE_SEL1 32 Analog Mode Select 1. See Table 6.

PDB 31 I, LVCMOS Power-Down Mode Input Pin

INTB 13 O, Open- Open Drain. Remote interrupt. Active LOW.

Drain Pull up to VDDIO with a 4.7kΩ resistor.

REM_INTB 40 O, Open- Remote interrupt. Mirrors status of INTB_IN from the deserializer.

Drain Note: External pull-up to 1.8V required. Recommended pull-up: 4.7kΩ.

INTB = H, Normal Operation

INTB = L, Interrupt Request

SPI PINS (DUAL LINK MODE ONLY)

MOSI 8 IO, LVCMOS SPI Master Out Slave In. Shared with D_GPIO0

MISO 10 IO, LVCMOS SPI Master In Slave Out. Shared with D_GPIO1

SPLK 11 IO, LVCMOS SPI Clock. Shared with D_GPIO2

SS 12 IO, LVCMOS SPI Slave Select. Shared with D_GPIO3

HIGH SPEED (HS) BIDIRECTIONAL CONTROL CHANNEL GPIO PINS (DUAL LINK MODE ONLY)

D_GPIO0 8 IO, LVCMOS HS GPIO0. Shared with MOSI

D_GPIO1 10 IO, LVCMOS HS GPIO1. Shared with MISO

D_GPIO2 11 IO, LVCMOS HS GPIO2. Shared with SPLK

D_GPIO3 12 IO, LVCMOS HS GPIO3. Shared with SS

Product Folder Links: DS90UB949-Q1

DS90UB949-Q1

www.ti.com

SNLS452 –NOVEMBER 2014

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NO.

BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS

GPIO0 4 IO, LVCMOS BCC GPIO0. Shared with SDIN

GPIO1 5 IO, LVCMOS BCC GPIO1. Shared with SWC

GPIO2 37 IO, LVCMOS BCC GPIO2. Shared with I2S_DC

GPIO3 38 IO, LVCMOS BCC GPIO3. Shared with I2S_DD

GPIO5_REG 36 IO, LVCMOS General Purpose Input/Output 5

Local register control only. Shared with I2S_DB

GPIO6_REG 35 IO, LVCMOS General Purpose Input/Output 6

Local register control only. Shared with I2S_DA

GPIO7_REG 33 IO, LVCMOS General Purpose Input/Output 7

Local register control only. Shared with I2S_WC

GPIO8_REG 34 IO, LVCMOS General Purpose Input/Output 8

Local register control only. Shared with I2S_CLK

SLAVE MODE LOCAL I2S CHANNEL PINS

I2S_WC 33 I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG

I2S_CLK 34 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG

I2S_DA 35 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG

I2S_DB 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG

I2S_DC 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2

I2S_DD 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3

AUXILIARY I2S CHANNEL PINS

SWC 5 O, LVCMOS Master Mode I2S Word Clock Ouput. Shared with GPIO1

SCLK 6 O, LVCMOS Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up

as I2CSEL, then it will switch to SCLK operation as an output.

SDIN 4 I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0

MCLK 16 IO, LVCMOS Master Mode I2S System Clock Input/Output

POWER and GROUND

VTERM 57 Power 3.3V (±5%) Supply for DC-coupled internal termination OR

1.8V (±5%) Supply for AC-coupled internal termination

Refer to Figure 25 or Figure 26.

VDD18 24 Power 1.8 (±5%) Analog supply. Refer to Figure 25 or Figure 26.

VDDA11 9 Power 1.1V(±5%) Analog supply. Refer to Figure 25 or Figure 26.

VDDHA11 52 Power 1.1V(±5%) TMDS supply. Refer to Figure 25 or Figure 26.

VDDHS11 21 Power 1.1V(±5%) supply. Refer to Figure 25 or Figure 26.

VDDL11 7 Power 1.1V(±5%) Digital supply. Refer to Figure 25 or Figure 26.

VDDP11 17 Power 1.1V(±5%) PLL supply. Refer to Figure 25 or Figure 26.

VDDS11 25 Power 1.1V(±5%) Serializer supply. Refer to Figure 25 or Figure 26.

VDDIO 3 Power 1.8V (±5%) IO supply. Refer to Figure 25 or Figure 26 .

GND Thermal GND Ground. Connect to Ground plane with at least 9 vias.

Pad

OTHER

RES0 2 Reserved. Tie to GND.

RES1 29

Product Folder Links: DS90UB949-Q1

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