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TI-DS90UB949-Q1.pdf
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FPD-Link III
2 Lane
VDDIO
1.8V
IDx
DOUT0+
DOUT0-
1.1V
IN_CLK-/+
HDMI
HPD
DDC
CEC
DOUT1+
DOUT1-
RIN0+
RIN0-
RIN1+
RIN1-
CLK+/-
CLK2+/-
FPD-Link
(Open LDI)
D0+/-
D1+/-
D2+/-
D3+/-
D4+/-
D5+/-
D6+/-
D7+/-
DS90UB949-Q1
Serializer
DS90UB948-Q1
Deserializer
IDx
D_GPIO
(SPI)
D_GPIO
(SPI)
LVDS
Display
1080p60
or Graphic
Processor
Graphics
Processor
IN_D0-/+
IN_D1-/+
IN_D2-/+
I2C
VDDIO
(3.3V / 1.8V)
3.3V
I2C
1.2V1.8V
HDMI ± High Definition Multimedia Interface
Product
Folder
Order
Now
Technical
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Tools &
Software
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Community
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNLS452
DS90UB949-Q1
ZHCSD34B –NOVEMBER 2014–REVISED AUGUST 2019
DS90UB949-Q1 1080p HDMI 转转 FPD-Link III 桥桥接接串串行行器器具具有有 HDCP 的的
具具有有 HDCP 的的
1
1 特特性性
1
• 符合面向汽车应用的 AEC-Q100 标准
– 器件温度等级 2:–40°C 至 +105°C,T
A
• TMDS 时钟高达 170MHz,支持 WUXGA
(1920x1200) 和 1080p60 分辨率(24 位色深)
• 单路和双路 FPD-Link III 输出
• 高清多媒体 (HDMI) v1.4b 输入
• HDMI 模式 DisplayPort (DP++) 输入
• 最多支持 8 通道的 HDMI 音频提取
• 高速反向通道,支持高达 2Mbps 的 GPIO
• 具有自动温度和老化补偿功能,支持长达 15 米的
电缆
• 可监视扩频输入时钟以降低 EMI
• 具有 1Mbps 快速模式增强版的 I2C(主/从)
• SPI 直通接口
• 向后兼容 DS90UB926Q-Q1 和 DS90UB928Q-Q1
FPD-Link III 解串器
2 应应用用
• 汽车信息娱乐系统:
– 车载信息娱乐 (IVI) 主机和人机交互界面 (HMI)
模块
– 后座娱乐系统
– 数字仪表组
• 监控摄像头
• 消费类输入 HDMI 端口
3 说说明明
DS90UB949-Q1 是一款 HDMI 到 FPD-Link III 桥接器
件,与 FPD-Link III DS90UB940-Q1/DS90UB948-Q1
解串器配合使用,可通过经济高效的 50Ω 单端同轴电
缆或 100Ω 差分屏蔽双绞线 (STP) 电缆提供单通道或
双通道高速串行流。该器件可串行化 HDMI v1.4b
输入,最高可支持 WUXGA 和 1080p60 视频分辨率
(24 位色深)。
FPD-Link III 接口支持通过同一条差分链路进行视频和
音频数据传输以及全双工控制(包括 I2C 和 SPI 通
信)。通过两个差分对实现视频数据和控制的整合可减
小互连线尺寸和重量,并简化系统设计。通过使用低压
差分信令、数据换序和随机生成更大限度地减少了电磁
干扰 (EMI)。在向后兼容模式下,该器件在单一差分链
路上最高可支持 WXGA 和 720p 分辨率(24 位色
深)。
DS90UB949-Q1 支持通过 HDMI 或外部 I2S 接口接收
多通道音频。该器件还提供可选的辅助音频接口。
器器件件信信息息
(1)
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
DS90UB949-Q1 VQFN (64) 9.00mm x 9.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
应应用用图图表表

2
DS90UB949-Q1
ZHCSD34B –NOVEMBER 2014–REVISED AUGUST 2019
www.ti.com.cn
Copyright © 2014–2019, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ..................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 DC Electrical Characteristics .................................... 7
6.6 AC Electrical Characteristics................................... 11
6.7 DC And AC Serial Control Bus Characteristics ...... 12
6.8 Recommended Timing for the Serial Control Bus .. 13
6.9 Timing Diagrams..................................................... 14
6.10 Typical Characteristics.......................................... 16
7 Detailed Description............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 32
7.5 Programming........................................................... 34
7.6 Register Maps......................................................... 38
8 Application and Implementation ........................ 68
8.1 Applications Information.......................................... 68
8.2 Typical Applications ................................................ 68
9 Power Supply Recommendations...................... 73
9.1 Power-Up Requirements and PDB Pin................... 73
10 Layout................................................................... 77
10.1 Layout Guidelines ................................................. 77
10.2 Layout Example .................................................... 78
11 器器件件和和文文档档支支持持 ..................................................... 79
11.1 文档支持 ............................................................... 79
11.2 接收文档更新通知 ................................................. 79
11.3 商标 ....................................................................... 79
11.4 静电放电警告......................................................... 79
11.5 Glossary................................................................ 79
12 机机械械、、封封装装和和可可订订购购信信息息....................................... 79
4 修修订订历历史史记记录录
Changes from Revision A (March 2019) to Revision B Page
• Changed V
DD11
maximum from 1.32 V back to 1.7 V............................................................................................................. 6
• 添加了
接收文档更新通知
部分 .............................................................................................................................................. 79
Changes from Original (November 2014) to Revision A Page
• Changed all references of HDMI Clock to TMDS Clock......................................................................................................... 3
• Changed V
DD11
maximum from: 1.7 V to: 1.32 V ................................................................................................................... 6
• Added RX_5V parameter to the Recommended Operating Conditions................................................................................. 7
• Added T
CLH1/2
and T
CHL1/2
parameters to the Recommended Operating Conditions .............................................................. 7
• Changed the TMDS jitter specification in the AC Electrical Characteristics table................................................................ 11
• Added additional HSCC information to the SPI Mode Configuration section....................................................................... 23
• Added information about using I2S with the DS90UH926-Q1 in the Audio Modes section................................................. 26
• Deleted Auto Soft Sleep mode from the MODE_SEL[1:0] Settings table ............................................................................ 32
• Added Frequency Detection Circuit section ......................................................................................................................... 34
• Added 5% resistor information to the Serial Control Bus section......................................................................................... 34
• Added information to Multi-Master Arbitration Support section ............................................................................................ 36
• Added additional information to register 0x01 ...................................................................................................................... 38
• Added registers 0x00, 0x13, 0x15, 0x5B, 0xC0, 0xC2, 0xC3, 0xC6, 0xC8, 0xCE, and 0xD0 to default list ....................... 38
• Changed information about GPIO0 modes x00 and x10 ..................................................................................................... 42
• Changed information about GPIO1 modes x00 and x10 ..................................................................................................... 43
• Added reset information to register 0x15 ............................................................................................................................. 47
• Changed the register 0x1A information................................................................................................................................ 48
• Added Registers 0x40, 0x41, and 0x42 ............................................................................................................................... 54
• Deleted Rev A1 silicon information....................................................................................................................................... 58
• Added 'Set to 0' test to the 0x5B register description........................................................................................................... 59

VDD18
VDDIO
SDIN / GPIO0
RES0
IN_D0-
VTERM
IN_D0+
VDDHA11
IN_D1-
IN_D1+
SCL
VDDHS11
VDD18
RES2
PDB
VDDA11
D_GPIO0 / MOSI
DOUT0-
DOUT0+
MCLK
VDDS11
DOUT1-
DOUT1+
IN_D2-
VDDHA11
CEC
IN_D2+
VDD18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDDHA11
I2S_DC / GPIO2
I2S_DD / GPIO3
VDDHA11
LFT
MODE_SEL0
IDx
RX_5V
IN_CLK-
IN_CLK+
VDDL11
X1
REM_INTB
SCLK / I2CSEL
VDDL11
RES1
VDDHS11
DDC_SDA
NC1
DDC_SCL
NC0
SDA
INTB
D_GPIO3 / SS
D_GPIO2 / SPLK
I2S_WC / GPIO7_REG
I2S_DB / GPIO5_REG
I2S_CLK / GPIO8_REG
I2S_DA / GPIO6_REG
D_GPIO1 / MISO
MODE_SEL1
NC2
HPD
SWC / GPIO1
DS90UB949-Q1
DAP = GND
VDDP11
VDDIO
64 VQFN
Top View
3
DS90UB949-Q1
www.ti.com.cn
ZHCSD34B –NOVEMBER 2014–REVISED AUGUST 2019
Copyright © 2014–2019, Texas Instruments Incorporated
• Changed register 0x5C[4:3] information. ............................................................................................................................. 60
• Added Page 0x10 Register................................................................................................................................................... 67
• Added Page 0x14 Register................................................................................................................................................... 67
• Changed graph caption from: 1080p60 Video at 2.6 Gbps Serial Line Rate (One of Two Lanes) to: 720p60 Video at
2.6-Gbps Serial Line Rate, Single Lane FPD-Link III Output............................................................................................... 72
• Changed Power-Up Requirements section .......................................................................................................................... 73
5 Pin Configuration and Functions
RGC Package
64-Pin VQFN
Top View
Pin Functions
PIN
I/O, TYPE DESCRIPTION
NAME NO.
HDMI TMDS INPUT
IN_CLK-
IN_CLK+
49
50
I, TMDS TMDS Clock Differential Input
IN_D0-
IN_D0+
55
56
I, TMDS TMDS Data Channel 0 Differential Input
IN_D1-
IN_D1+
59
60
I, TMDS TMDS Data Channel 1 Differential Input

4
DS90UB949-Q1
ZHCSD34B –NOVEMBER 2014–REVISED AUGUST 2019
www.ti.com.cn
Copyright © 2014–2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O, TYPE DESCRIPTION
NAME NO.
IN_D2-
IN_D2+
62
63
I, TMDS TMDS Data Channel 2 Differential Input
OTHER HDMI
HPD 42 O, Open-
Drain
Hot Plug Detect Output. Pull up to RX_5V with a 1-kΩ resistor
RX_5V 43 I HDMI 5-V Detect Input
DDC_SDA 44 IO, Open-
Drain
DDC Slave Serial Data
Pullup to RX_5V with a 47-kΩ resistor
DDC_SCL 45 I, Open-Drain DDC Slave Serial Clock
Pullup to RX_5V with a 47-kΩ resistor
CEC 1 IO, Open-
Drain
Consumer Electronic Control Channel Input/Output Interface.
Pullup with a 27-kΩ resistor to 3.3 V
X1 39 I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be
connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level
1.8 V. Leave it open if unused.
FPD-LINK III SERIAL
DOUT0- 26 O FPD-Link III Inverting Output 0
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers
and 33-nF capacitor for 94x deserializers
DOUT0+ 27 O FPD-Link III True Output 0
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers
and 33-nF capacitor for 94x deserializers
DOUT1- 22 O FPD-Link III Inverting Output 1
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers
and 33-nF capacitor for 94x deserializers
DOUT1+ 23 O FPD-Link III True Output 1
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers
and 33-nF capacitor for 94x deserializers
LFT 20 Analog FPD-Link III Loop Filter
Connect to a 10-nF capacitor to GND
CONTROL
SDA 14 IO, Open-
Drain
I2C Data Input / Output Interface
Open-drain. Must have an external pullup to resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO
NOT FLOAT.
Recommended pullup: 4.7 kΩ.
SCL 15 IO, Open-
Drain
I2C Clock Input / Output Interface
Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO
NOT FLOAT.
Recommended pullup: 4.7 kΩ.
I2CSEL 6 I, LVCMOS I2C Voltage Level Strap Option
Tie to V
DDIO
with a 10-kΩ resistor for 1.8-V I2C operation.
Leave floating for 3.3-V I2C operation.
This pin is read as an input at power up.
IDx 19 Analog I2C Serial Control Bus Device ID Address Select
MODE_SEL0 18 Analog Mode Select 0. See Table 6.
MODE_SEL1 32 Analog Mode Select 1. See Table 6.
PDB 31 I, LVCMOS Power-Down Mode Input Pin
INTB 13 O, Open-
Drain
Open Drain. Remote interrupt. Active LOW.
Pullup to VDDIO with a 4.7-kΩ resistor.
REM_INTB 40 O, Open-
Drain
Remote interrupt. Mirrors status of INTB_IN from the deserializer.
Note: External pullup to 1.8 V required. Recommended pullup: 4.7 kΩ.
INTB = H, Normal Operation
INTB = L, Interrupt Request
SPI PINS (DUAL LINK MODE ONLY)
MOSI 8 IO, LVCMOS SPI Master Out Slave In. Shared with D_GPIO0

5
DS90UB949-Q1
www.ti.com.cn
ZHCSD34B –NOVEMBER 2014–REVISED AUGUST 2019
Copyright © 2014–2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O, TYPE DESCRIPTION
NAME NO.
MISO 10 IO, LVCMOS SPI Master In Slave Out. Shared with D_GPIO1
SPLK 11 IO, LVCMOS SPI Clock. Shared with D_GPIO2
SS 12 IO, LVCMOS SPI Slave Select. Shared with D_GPIO3
HIGH-SPEED (HS) BIDIRECTIONAL CONTROL CHANNEL GPIO PINS (DUAL LINK MODE ONLY)
D_GPIO0 8 IO, LVCMOS HS GPIO0. Shared with MOSI
D_GPIO1 10 IO, LVCMOS HS GPIO1. Shared with MISO
D_GPIO2 11 IO, LVCMOS HS GPIO2. Shared with SPLK
D_GPIO3 12 IO, LVCMOS HS GPIO3. Shared with SS
BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS
GPIO0 4 IO, LVCMOS BCC GPIO0. Shared with SDIN
GPIO1 5 IO, LVCMOS BCC GPIO1. Shared with SWC
GPIO2 37 IO, LVCMOS BCC GPIO2. Shared with I2S_DC
GPIO3 38 IO, LVCMOS BCC GPIO3. Shared with I2S_DD
REGISTER-ONLY GPIO
GPIO5_REG 36 IO, LVCMOS General-Purpose Input/Output 5
Local register control only. Shared with I2S_DB
GPIO6_REG 35 IO, LVCMOS General-Purpose Input/Output 6
Local register control only. Shared with I2S_DA
GPIO7_REG 33 IO, LVCMOS General-Purpose Input/Output 7
Local register control only. Shared with I2S_WC
GPIO8_REG 34 IO, LVCMOS General-Purpose Input/Output 8
Local register control only. Shared with I2S_CLK
SLAVE MODE LOCAL I2S CHANNEL PINS
I2S_WC 33 I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG
I2S_CLK 34 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG
I2S_DA 35 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG
I2S_DB 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG
I2S_DC 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2
I2S_DD 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3
AUXILIARY I2S CHANNEL PINS
SWC 5 O, LVCMOS Master Mode I2S Word Clock Output. Shared with GPIO1
SCLK 6 O, LVCMOS Master Mode I2S Clock Output. Shared with I2CSEL. This pin is sampled following power-
up as I2CSEL, then it will switch to SCLK operation as an output.
SDIN 4 I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0
MCLK 16 IO, LVCMOS Master Mode I2S System Clock Input/Output
POWER AND GROUND
VTERM 57 Power 3.3-V (±5%) Supply for DC-coupled internal termination OR
1.8-V (±5%) Supply for AC-coupled internal termination
Refer to Figure 25 or Figure 26.
VDD18 24
51
64
Power 1.8-V (±5%) Analog supply. Refer to Figure 25 or Figure 26.
VDDA11 9 Power 1.1-V (±5%) Analog supply. Refer to Figure 25 or Figure 26.
VDDHA11 52
54
58
61
Power 1.1-V (±5%) TMDS supply. Refer to Figure 25 or Figure 26.
VDDHS11 21
28
Power 1.1-V (±5%) supply. Refer to Figure 25 or Figure 26.
VDDL11 7
41
Power 1.1-V (±5%) Digital supply. Refer to Figure 25 or Figure 26.
剩余87页未读,继续阅读
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