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DS90UB953-Q1
ZHCSGW1B –SEPTEMBER 2017 –REVISED SEPTEMBER 2018
www.ti.com.cn
版权 © 2017–2018, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 5
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 8
6.5 Electrical Characteristics........................................... 9
6.6 Recommended Timing for the Serial Control Bus .. 13
6.7 Timing Diagrams..................................................... 14
6.8 Typical Characteristics............................................ 14
7 Detailed Description............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 22
7.5 Programming........................................................... 26
7.6 Pattern Generation ................................................. 28
7.7 Register Maps ........................................................ 32
8 Application and Implementation ........................ 69
8.1 Application Information............................................ 69
8.2 Typical Applications ................................................ 72
9 Power Supply Recommendations...................... 75
9.1 Power-Up Sequencing ............................................ 75
9.2 Power Down (PDB)................................................. 76
10 Layout................................................................... 76
10.1 Layout Guidelines ................................................. 76
10.2 Layout Examples................................................... 77
11 器器件件和和文文档档支支持持 ..................................................... 80
11.1 器件支持................................................................ 80
11.2 文档支持 ............................................................... 80
11.3 接收文档更新通知 ................................................. 80
11.4 社区资源................................................................ 80
11.5 商标 ....................................................................... 80
11.6 静电放电警告......................................................... 80
11.7 术语表 ................................................................... 80
12 机机械械、、封封装装和和可可订订购购信信息息....................................... 81
4 修修订订历历史史记记录录
Changes from Revision A (February 2018) to Revision B Page
• Updated GPIO pin descriptions. ............................................................................................................................................ 6
• Replace CLK_IN with clock throughout document. ............................................................................................................... 6
• Changed Supply voltage from 2.5V to 2.16V ......................................................................................................................... 7
• Changed asynchronous to non-synchronous......................................................................................................................... 8
• Deleted "for synchronous mode" ............................................................................................................................................ 8
• Added internal reference frequency in EC table................................................................................................................... 10
• Added Internal AON Clock to Block Diagram....................................................................................................................... 15
• 已更改 mode to modes. ....................................................................................................................................................... 18
• Changed 130ns to 225ns. .................................................................................................................................................... 22
• Changed latency to 1.5us and jitter to 0.7us. ...................................................................................................................... 22
• Changed CLK_IN Mode to Modes. ..................................................................................................................................... 22
• Added DVP Mode ................................................................................................................................................................ 22
• Changed table formatting. ................................................................................................................................................... 23
• 已更改 REFLCK to Back Channel ....................................................................................................................................... 23
• 已添加 Frequency for Synchronous Mode .......................................................................................................................... 23
• 已更改 naming convention from "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN" mode column dor
CLKIN_DIV = 2..................................................................................................................................................................... 23
• 已更改 from CLK_IN to Back Channel (Half Rate)............................................................................................................... 23
• 已添加 Non-Synchronous Internal Clock Mode ................................................................................................................... 23
• 已更改 the value from 24.2 - 25.5 MHz to 48.4 - 51 MHz ................................................................................................... 23
• 已更改 the value from 25 - 52 MHz to 24.2 to 25.5 MHz .................................................................................................... 23
• Added DVP External Clock................................................................................................................................................... 23
• 已添加 text "Deserializer Mode" to clarify mode RAW10 .................................................................................................... 23
• 已添加 additional information to note. ................................................................................................................................. 23
