DS90UB913/DS90UB914datasheet_DS90UB960是什么资源-CSDN文库

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DS90UB913A-Q1和DS90UB914A-Q1是德州仪器公司（Texas Instruments）生产的针对汽车行业应用的高速串行器和解串器（Serializer/Deserializer）芯片，支持FPD-Link III技术。该芯片集成了多种通信特性，使其在连接ECU（电子控制单元）中的图像传感器和视频处理器时具备高效的数据传输能力。下面将详细介绍它们的关键特性和应用场景。标题中提到的“DS90UB913/DS90UB914 datasheet”指的是该芯片的数据手册。数据手册是对半导体器件详细的技术描述，包含了操作参数、电气特性和应用信息等内容，是了解和使用该芯片不可或缺的参考资料。描述部分提到的“25 to100 MHz 10/12-Bit FPD-Link III Serializer and Deserializer”指出了该芯片的主要特点：支持25 MHz到100 MHz的输入像素时钟频率，具有10位和12位两种数据负载选项。FPD-Link III是德州仪器公司推出的高速串行接口技术，用于长距离、高性能的视频数据传输。标签部分的“LVDS DS90UB913 DS90UB914”提到了低压差分信号（Low-Voltage Differential Signaling，简称LVDS）技术，它是一种差分信号技术，用于高速数据传输，具有低功耗、低辐射和良好的抗干扰能力。DS90UB913和DS90UB914芯片支持LVDS技术，确保了在高速通信时的可靠性和性能。在提供的部分内容中，芯片特性包括： 1. 支持25MHz到100MHz的输入像素时钟频率，适用于不同的图像处理需求。 2. 支持同轴或单差分对互连，提供灵活的物理层连接选择。 3. 具有可编程的数据载荷，10位数据载荷支持高达100MHz，12位数据载荷支持高达75MHz。 4. 提供连续的低延迟双向控制接口通道，并支持I2C协议，最大时钟频率为400kHz。 5. 2:1的复用器可允许在两个输入图像间进行选择，单一时钟域支持接收均衡器自动适应不同电缆损耗的变化。 6. 4个通用目的输入（GPI）/输出（GPO），LOCK输出报告引脚以及SPEED BIST诊断特性，用于验证链路完整性。 7. 1.8V、2.8V或3.3V兼容的并行输入，单电源为1.8V。 8. 符合ISO10605和IEC61000-4-2标准的静电放电（ESD）保护，适合汽车应用。 9. 自动温度范围为-40°C至+105°C的汽车级产品，满足AEC-Q100 Grade 2的要求。 10. 小巧的 Serialize 器芯片（5mm x 5mm）封装。 11. EMI/EMC缓解措施，包括可编程的扩展频谱（SSCG）输出和接收器交错输出。应用方面，DS90UB913A-Q1/DS90UB914A-Q1芯片适用于汽车的前视或后视摄像头，以实现防撞减缓和停车辅助的环绕视图。 DS90UB913A-Q1/DS90UB914A-Q1芯片组通过FPD-Link III技术，能够高效处理高速视频数据，支持差分信号和LVDS技术，为汽车电子控制单元提供稳定可靠的图像和视频数据传输解决方案。

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DS90UB913A-Q1, DS90UB914A-Q1

www.ti.com

SNLS443A –MAY 2013–REVISED JUNE 2013

DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit

FPD-Link III Serializer and Deserializer

Check for Samples: DS90UB913A-Q1, DS90UB914A-Q1

FEATURES

DESCRIPTION

The DS90UB913A-Q1/DS90UB914A-Q1 chipset

• 25 MHz to 100 MHz Input Pixel Clock Support

offers a FPD-Link III interface with a high-speed

• Coaxial or Single Differential Pair Interconnect

forward channel and a bidirectional control channel

• Programmable Data Payload:

for data transmission over a single coaxial cable or

differential pair. The DS90UB913A-Q1/914A-Q1

– 10-bit Payload up to 100 Mhz

chipset incorporates differential signaling on both the

– 12-bit Payload up to 75 MHz

high-speed forward channel and bidirectional control

• Continuous Low Latency Bidirectional Control

channel data paths. The serializer/deserializer pair is

Interface Channel with I2C™ Support @400

targeted for connections between imagers and video

kHz

processors in an ECU (Electronic Control Unit). This

chipset is ideally suited for driving video data

• 2:1 Multiplexer to choose between two input

requiring up to 12-bit pixel depth plus two

images

synchronization signals along with bidirectional

• Embedded Clock with DC-balanced Coding to

control channel bus.

Support AC-coupled Interconnects

The deserializer features a multiplexer to allow

• Capable of Driving up to 15m Coaxial or 20m

selection between two input imagers, one active at a

Shielded Twisted-pair Cables

time. The primary video transport converts 10-bit or

• Receive Equalizer Automatically Adapts for

12-bit data to a single high-speed serial stream, along

with a separate low latency bidirectional control

Changes in Cable Loss

channel transport that accepts control information

• 4 Dedicated General Purpose Input (GPI)/

from an I2C port and is independent of video blanking

Output (GPO)

period.

• LOCK Output Reporting Pin and @SPEED

Using TI’s embedded clock technology allows

BIST Diagnosis Feature to Validate Link

transparent full-duplex communication over a single

Integrity

differential pair, carrying asymmetrical bidirectional

• 1.8V, 2.8V or 3.3V-Compatible Parallel Inputs

control channel information in both directions. This

on Serializer

single serial stream simplifies transferring a wide data

bus over PCB traces and cable by eliminating the

• Single Power Supply at 1.8V

skew problems between parallel data and clock

• ISO 10605 and IEC 61000-4-2 ESD Compliant

paths. This significantly saves system cost by

• Automotive Grade Product: AEC-Q100 Grade 2

narrowing data paths that in turn reduce PCB layers,

qualified

cable width, and connector size and pins. In addition,

the Deserializer inputs provide adaptive equalization

• Temperature Range −40°C to +105°C

to compensate for loss from the media over longer

• Small Serializer Rootprint (5mm x 5mm)

distances. Internal DC-balanced encoding/decoding is

• EMI/EMC Mitigation - Deserializer

used to support AC-coupled interconnects. The

DS90UB913A-Q1 serializer is offered in a 32-pin

– Programmable Spread Spectrum (SSCG)

WQFN package and the DS90UB914A-Q1

Outputs

deserializer is offered in a 48-pin WQFN package.

– Receiver Staggered Outputs

APPLICATIONS

• Front or Rear-View Camera for Collision

Mitigation

• Surround View for Parking Assistance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2I2C is a trademark of Philips Semiconductor Corp..

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90UB913A-Q1, DS90UB914A-Q1

SNLS443A –MAY 2013–REVISED JUNE 2013

www.ti.com

Table 1. Pin Descriptions (continued)

Pin Name Pin No. I/O, Type Description

GPO[3]/CLKIN 18 Input/Output, GPO3 can be configured to be the output for input signals coming from the GPIO3

LVCMOS pin on the Deserializer or can be configured to be the output of the local register

setting on the Serializer. It can also be configured to be the input clock pin when

the DS90UB913A-Q1 Serializer is working with an external oscillator. See

Applications Information section for a detailed description of the

DS90UB913A/914A chipsets working with an external oscillator.

BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE

Input/Output, Clock line for the bidirectional control bus communication.

SCL 4

Open Drain SCL requires an external pull-up resistor to V

DDIO

Input/Output, Data line for the bidirectional control bus communication.

SDA 5

Open Drain SDA requires an external pull-up resistor to V

DDIO

Device mode select.

Input, LVCMOS Resistor to Ground and 10 kΩ pull-up to 1.8V rail. MODE pin on the Serializer can

MODE 8

w/ pull down be used to select whether the system is running off the PCLK from the imager or

an external oscillator. See details in Table 7.

Device ID Address Select.

ID[x] 6 Input, analog The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor

to Ground and 10 kΩ pull-up to 1.8V rail. See Table 9.

CONTROL AND CONFIGURATION

Power down Mode Input Pin.

PDB = H, Serializer is enabled and is ON.

Input, LVCMOS

PDB 9 PDB = L, Serializer is in Power Down mode. When the Serializer is in Power

w/ pull down

Down, the PLL is shutdown, and IDD is minimized. Programmed control register

data are NOT retained and reset to default values.

Input, LVCMOS Reserved.

RES 7

w/ pull down This pin MUST be tied LOW.

FPD–Link III INTERFACE

Input/Output, Non-inverting differential output, bidirectional control channel input. The

DOUT+ 13

CML interconnect must be AC Coupled with a 0.1µF capacitor.

DOUT- 12 Input/Output, Inverting differential output, bidirectional control channel input. The interconnect

CML must be AC Coupled with a 0.1µF capacitor. For applications using single-ended

coaxial interconnect, terminate to Ground with a 0.047µF capacitor.

POWER AND GROUND

VDDPLL 10 Power, Analog PLL Power, 1.8V ±5%.

VDDT 11 Power, Analog Tx Analog Power, 1.8V ±5%.

VDDCML 14 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%.

VDDD 28 Power, Digital Digital Power, 1.8V ±5%.

Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from

VDDIO 25

DDIO

. V

DDIO

can be connected to a 1.8V ±5% or 2.8±10% or 3.3V ±10%.

Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located

VSS DAP at the center of the WQFN package. Connected to the ground plane (GND) with at

least 9 vias.

Product Folder Links: DS90UB913A-Q1 DS90UB914A-Q1

DS90UB914AQ

48-Pin WQFN

(Top View)

ROUT[10]

ROUT[11]

VSYNC

PCLK

OEN

OSS_SEL

SCL

SDA

GPIO[3]

GPIO[2]

GPIO[0]

VDDIO1

RIN1+

RIN1-

IDx[0]

VDDR

VDDSSCG

BISTEN

VDDIO3

HSYNC GPIO[1]

VDDCML1

IDx[1]

ROUT[9]

ROUT[7]

ROUT[2]

ROUT[0]

ROUT[8]

ROUT[1]

ROUT[6]

VDDD

ROUT[5]

LOCK

PDB

VDDPLL

RES

RIN0-

RIN0+

VDDCML0

CMLOUTN

CMLOUTP

PASS

MODE

ROUT[4]

ROUT[3]

VDDIO2

DAP = GND

SEL

DS90UB913A-Q1, DS90UB914A-Q1

www.ti.com

SNLS443A –MAY 2013–REVISED JUNE 2013

DS90UB914A-Q1 Pin Diagram

Figure 5. Deserializer - DS90UB914A-Q1 — Top View

DS90UB914A-Q1 Deserializer Pin Descriptions

Table 2. Pin Descriptions

Pin Name Pin No. I/O, Type Description

LVCMOS PARALLEL INTERFACE

ROUT[11:0] 11,12,13,14, Outputs, Parallel Data Outputs.

15,16,18,19, LVCMOS

21,22,23,24

Horizontal SYNC Output. Note: HS transition restrictions: 1. 12-bit Low-Frequency

Output, mode: No HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions

HSYNC 10

LVCMOS (raw) 3. 10-bit High-Frequency mode: HS restricted to no more than one transition per

10 PCLK cycles.

Vertical SYNC Output. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode:

Output, No VS restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3.

VSYNC 9

LVCMOS 10-bit High-Frequency mode: VS restricted to no more than one transition per 10

PCLK cycles.

Output, Pixel Clock Output Pin.

PCLK 8

LVCMOS Strobe edge set by RRFB control register.

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

General-purpose input/output pins can be used to control and respond to various

Digital

commands. They may be configured to be the input signals for the corresponding

GPI0[1:0] 27,28 Input/Output,

GPOs on the serializer or they may be configured to be outputs to follow local register

LVCMOS

settings.

General purpose input/output pins GPO[3:2] can be configured to be input signals for

Digital GPOs on the Serializer. In addition they can also be configured to be outputs to follow

GPIO[3:2] 25,26 Input/Output the local register settings. When the SerDes chipsets are working with an external

LVCMOS oscillator, these pins can be configured only to be outputs to follow the local register

settings.

Product Folder Links: DS90UB913A-Q1 DS90UB914A-Q1

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