2
DS90UB913A-Q1
ZHCSEW6F –MAY 2013 –REVISED JANUARY 2020
www.ti.com.cn
版权 © 2013– 2020, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Device Comparison Table..................................... 5
6 Pin Configuration and Functions......................... 5
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 8
7.5 Electrical Characteristics........................................... 8
7.6 Recommended Serializer Timing For PCLK .......... 11
7.7 AC Timing Specifications (SCL, SDA) - I2C-
Compatible............................................................... 12
7.8 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C-Compatible ................................. 12
7.9 Timing Diagrams..................................................... 13
7.10 Serializer Switching Characteristics...................... 15
7.11 Typical Characteristics.......................................... 16
8 Detailed Description............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 21
8.5 Programming .......................................................... 26
8.6 Register Maps......................................................... 30
9 Application and Implementation ........................ 37
9.1 Application Information............................................ 37
9.2 Typical Applications ................................................ 39
10 Power Supply Recommendations ..................... 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 45
12 器器件件和和文文档档支支持持 ..................................................... 47
12.1 文档支持................................................................ 47
12.2 接收文档更新通知 ................................................. 47
12.3 支持资源................................................................ 47
12.4 商标 ....................................................................... 47
12.5 静电放电警告......................................................... 47
12.6 Glossary................................................................ 47
13 机机械械、、封封装装和和可可订订购购信信息息....................................... 47
4 修修订订历历史史记记录录
Changes from Revision E (September 2018) to Revision F Page
• Clarified GPO2 description by removing statement about leaving pin open if unused ......................................................... 6
• Added register 0x27[5] to register map ............................................................................................................................... 35
• Fixed missing register 0x29 typo ......................................................................................................................................... 36
• Added maximum power up timing constraint between VDD_n and PDB ........................................................................... 37
• Added recommended software programming steps if VDD_n to PDB maximum power up timing constraint can not
be met .................................................................................................................................................................................. 38
Changes from Revision D (October 2016) to Revision E Page
• Added recommendation to ensure GPO2 is low when PDB goes high ................................................................................ 6
• Added Power Over Coax supply noise to the recommended operating conditions table ...................................................... 8
• Clarified PCLK clock frequency range and added external clock input frequency range ...................................................... 8
• Added strap pin input current specification for MODE and IDX pins .................................................................................... 9
• Updated T
JIT1
PCLK input jitter in the external oscillator mode ........................................................................................... 11
• Added clarification on MODE pin description in PCLK from imager mode ......................................................................... 22
• Updated pullup and pulldown resistor to R
1
and R
2
in MODE pin configuration diagram ................................................... 22
• Updated the MODE setting values to ratio........................................................................................................................... 23
• Updated pullup and pulldown resistor for IDX to R
3
and R
4
in the diagram......................................................................... 28
• Updated IDX setting values to ratio ..................................................................................................................................... 28
• Updated register "TYPE" column per legend ...................................................................................................................... 30
• Added type and default value to the reserved register bits that were missing this information .......................................... 30
• Added that register 0x00[7:1] does not auto update IDX strapped address ....................................................................... 30
• Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b) ............................................................... 32
• Clarified description on PDB pin usage during power up .................................................................................................... 37
