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30 mA30 mA
4/3
12-Bit Shift Register
LED Driver
MCU Serial I/F
Battery 9 V–40 V
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS141
TLC6C5912-Q1
ZHCS301C –DECEMBER 2012–REVISED JULY 2016
TLC6C5912-Q1 电电源源逻逻辑辑 12 通通道道移移位位寄寄存存器器 LED 驱驱动动器器
1
1 特特性性
1
• 适用于汽车电子 应用
• 宽 V
CC
电压范围:3.5V 至 5.5V
• 40V 的最大输出额定值
• 12 个功率 DMOS 晶体管输出,
V
CC
= 5V 时的连续电流输出达 50mA
• 热关断保护
• 针对多级的增强型级联
• 所有寄存器由单一输入清零
• 低功耗
• 缓开关时间(t
r
和 t
f
),这十分有助于减少电磁干扰
(EMI)
• 20 引脚薄型小外形尺寸 (TSSOP)-PW 封装
• 20 引脚 DW 封装
2 应应用用
• 仪表板
• 信号灯
• LED 照明和控制
3 说说明明
TLC6C5912-Q1 是一款单片、中等电压、低电流电源
12 位移位寄存器,设计用于需要相对适量负载功率的
系统(如 LED)中。
此器件包含一个 12 位串入、并出移位寄存器,此寄存
器为一个 12 位 D 类存储寄存器提供数据。移位和存
储寄存器之间的数据传输分别在移位寄存器时钟
(SRCK) 和寄存器时钟 (RCK) 的上升边沿上发生。当
移位寄存器清零 (CLR) 为高电平时,存储寄存器将数
据传输到输出缓冲器 。一个CLR上的低电平将器件中
的所有寄存器清零。将输出使能 (G) 保持为高电平将
把输出缓冲器中的所有数据保存为低电平,并且所有漏
极输出关闭。保持G为低电平将使得来自存储寄存器中
的数据对于输出缓冲器不可见。
当输出缓冲器中的数据为低电平时,DMOS 晶体管的
输出被关闭。当数据为高电平时,DMOS 晶体管输出
具有电流吸收功能。串行输出 (SER OUT) 在 SRCK
的下降沿随时钟移出器件,为级联应用提供更多保持
时间。这对于时钟信号可能出现偏移的应用、 放置位
置相互不靠近的器件、 或者电磁干扰较大的系统而言
可以提升性能。此器件内置有热关断保护。
输出端为低侧开漏 DMOS 晶体管,输出额定电压为
40V,V
CC
= 5V 时拥有 50mA 的连续灌电流能力。电
流限值随着结温上升而降低,从而提供额外的器件保
护。该器件还提供高达 2000V 的 ESD 人体模型保护
和 200V 的 ESD 机器模型保护。
TLC6C5912-Q1 的额定运行环境温度范围为 -40°C 至
125°C。
器器件件信信息息
(1)
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
TLC6C5912-Q1
SOIC (20) 12.80mm x 7.50mm
TSSOP (20) 6.50mm × 4.40mm
(1) 要了解所有可用封装,请参见数据表末尾的可订购产品附录。
典典型型应应用用电电路路原原理理图图
2
TLC6C5912-Q1
ZHCS301C –DECEMBER 2012 –REVISED JULY 2016
www.ti.com.cn
Copyright © 2012–2016, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 7
7 Parameter Measurement Information .................. 9
8 Detailed Description............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 器器件件和和文文档档支支持持 ..................................................... 16
12.1 接收文档更新通知 ................................................. 16
12.2 社区资源................................................................ 16
12.3 商标 ....................................................................... 16
12.4 静电放电警告......................................................... 16
12.5 Glossary................................................................ 16
13 机机械械、、封封装装和和可可订订购购信信息息....................................... 16
4 修修订订历历史史记记录录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision B (December 2015) to Revision C Page
• Changed r
DS(on)
test condition from 50 mA to 20 mA.............................................................................................................. 5
• 已添加
接收文档更新通知
部分 ............................................................................................................................................... 16
Changes from Revision A (January 2013) to Revision B Page
• 已添加
引脚配置和功能
部分,ESD
额定值
表,
特性 描述
部分,
器件功能模式
,
应用和实施
部分,
电源相关建议
部
分,
布局
部分,
器件和文档支持
部分以及
机械、封装和可订购信息
部分 ................................................................................ 1
Changes from Original (December 2012) to Revision A Page
• 已将器件状态从“产品预览”改为“量产数据”.............................................................................................................................. 1
1VCC 20 GND
2SER IN 19 SRCK
3DRAIN0 18 DRAIN11
4DRAIN1 17 DRAIN10
5DRAIN2 16 DRAIN9
6DRAIN3 15 DRAIN8
7DRAIN4 14 DRAIN7
8DRAIN5 13 DRAIN6
9CLR 12 RCK
10G 11 SER OUT
Not to scale
1VCC 20 GND
2SER IN 19 SRCK
3DRAIN0 18 DRAIN11
4DRAIN1 17 DRAIN10
5DRAIN2 16 DRAIN9
6DRAIN3 15 DRAIN8
7DRAIN4 14 DRAIN7
8DRAIN5 13 DRAIN6
9CLR 12 RCK
10G 11 SER OUT
Not to scale
3
TLC6C5912-Q1
www.ti.com.cn
ZHCS301C –DECEMBER 2012 –REVISED JULY 2016
Copyright © 2012–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
DW Package
20-Pin SOIC
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
CLR 9 I
Shift register clear, active-low: CLR is the signal used to clear all the registers. The
storage register transfers data to the output buffer when shift register clear CLR is high.
Driving CLR is low clears all the registers in the device.
DRAIN0 3 O
Open-drain output: DRAIN0 to DRAIN11 are the LED current-sink channels. These pins
connect to the LED cathodes, and they can survive up to 40-V LED supply voltage. This is
quite helpful during automotive load-dump conditions.
DRAIN1 4 O
DRAIN2 5 O
DRAIN3 6 O
DRAIN4 7 O
DRAIN5 8 O
DRAIN6 13 O
DRAIN7 14 O
DRAIN8 15 O
DRAIN9 16 O
DRAIN10 17 O
DRAIN11 18 O
G 10 I
Output enable, active-low: G is the LED channel enable and disable input pin. Having G
low enables all drain channels according to the output-latch register content. When high, all
channels are off.
GND 20 —
Power ground: GND is the ground reference pin for the device. This pin must connect to the
ground plane on the PCB.
RCK 12 I
Register clock: RCK is the storage register clock. The data in each shift register stage
transfers to the storage register at the rising edge of RCK. Data in the storage register
appears at the output whenever the output enable G input signal is high.
SER IN 2 I
Serial-data input: SER IN is the serial data input. Data on SER IN loads into the internal
register on each rising edge of SRCK.
4
TLC6C5912-Q1
ZHCS301C –DECEMBER 2012 –REVISED JULY 2016
www.ti.com.cn
Copyright © 2012–2016, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
SER OUT 11 O
Serial-data output: SER OUT is the serial data output of the 12−bit serial shift register. The
purpose of this pin is to cascade several devices on the serial bus. By connecting the SER
OUT pin to the SER IN input of the next device on the serial bus to cascade, the data
transfers to the next device on the falling edge of SRCK. This can improve the cascade
application reliability, as it can avoid the issue that the second device receives SRCK and
data input at the same rising edge of SRCK.
SRCK 19 I
Shift-register clock: SRCK is the serial clock input. On each rising SRCK edge, data
transfers from SER IN to the internal serial shift registers.
V
CC
1 I
Power supply: V
CC
is the power supply pin voltage for the device. TI recommends adding a
0.1 μF ceramic capacitor close to the pin.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
V
CC
Logic supply voltage 8 V
V
I
Logic input-voltage –0.3 8 V
V
DS
Power DMOS drain-to-source voltage 42 V
Continuous total dissipation See Thermal Information
Operating ambient temperature (Top) 125 °C
T
J
Operating junction temperature –40 150 °C
T
stg
Storage temperature –55 165 °C
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002
(1)
±2000
V
Charged device model (CDM), per AEC Q100-011 ±750
6.3 Recommended Operating Conditions
MIN MAX UNIT
V
CC
Supply voltage 3 5.5 V
V
IH
High-level input voltage 2.4 V
V
IL
Low-level input voltage 0.7 V
t
su
Setup time, SER IN high before SRCK↑ 15 ns
t
h
Hold time, SER IN high after SRCK↑ 15 ns
t
w
Pulse duration 40 ns
T
C
Operating case temperature –40 125 °C
5
TLC6C5912-Q1
www.ti.com.cn
ZHCS301C –DECEMBER 2012 –REVISED JULY 2016
Copyright © 2012–2016, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC
(1)
TLC6C5912-Q1
UNIT20 PINS
PW (TSSOP) DW (SOIC)
R
θJA
Junction-to-ambient thermal resistance 114.8 81.2 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 44.1 45.4 °C/W
R
θJB
Junction-to-board thermal resistance 61.3 49.1 °C/W
ψ
JT
Junction-to-top characterization parameter 4.7 17.5 °C/W
ψ
JB
Junction-to-board characterization parameter 60.8 48.6 °C/W
6.5 Electrical Characteristics
V
CC
= 5 V, T
C
= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRAIN0 to DRAIN11,
drain-to-source voltage
40 V
V
OH
High-level output voltage,
SER OUT
I
OH
= –20 μA
V
CC
= 5 V
4.9 4.99
V
I
OH
= –4 mA 4.5 4.69
V
OL
Low-level output voltage,
SER OUT
I
OH
= 20 μA
V
CC
= 5 V
0.001 0.01
V
I
OH
= 4 mA 0.25 0.4
I
IH
High-level input current V
CC
= 5 V, V
I
= V
CC
0.2 μA
I
IL
Low-level input current V
CC
= 5 V, V
I
= 0 –0.2 μA
I
CC
Logic supply current
V
CC
= 5 V,
No clock signal
All outputs off 0.1 1
μA
All outputs on 130 170
I
CC(FRQ)
Logic supply current at
frequency
f
SRCK
= 5 MHz, C
L
= 30 pF, all outputs on 300 µA
I
DSX
Off-state drain current
V
DS
= 30 V, V
CC
= 5 V 0.1
μA
V
DS
= 30 V, T
C
= 125°C, V
CC
= 5 V 0.15 0.3
r
DS(on)
Static drain-source on-state
resistance
I
D
= 20 mA, V
CC
= 5 V, T
A
= 25°C, single channel ON 6 7.4 8.6
Ω
I
D
= 20 mA, V
CC
= 5 V, T
A
= 25°C, all channels ON 6.7 8.9 9.6
I
D
= 20 mA, V
CC
= 3.3 V, T
A
= 25°C, single channel ON 7.9 9.3 11.2
I
D
= 20 mA, V
CC
= 3.3 V, T
A
= 25°C, all channels ON 8.7 10.6 12.3
I
D
= 20 mA, V
CC
= 5 V, T
A
= 125°C, single channel ON 9.1 11.2 12.9
I
D
= 20 mA, V
CC
= 5 V, T
A
= 125°C, all channels ON 10.3 13 14.5
I
D
= 20 mA, V
CC
= 3.3 V, T
A
= 125°C, single channel ON 11.6 13.7 16.4
I
D
= 20 mA, V
CC
= 3.3 V, T
A
= 125°C, all channels ON 12.8 15.6 18.2
T
SHUTDOWN
Thermal shutdown trip point 150 175 200 °C
T
HYS
Hysteresis 15 °C
6.6 Switching Characteristics
V
CC
= 5 V, T
J
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output from G
C
L
= 30 pF, I
D
= 48 mA
210 ns
t
PHL
Propagation delay time, high-to-low-level output from G 75 ns
t
r
Rise time, drain output 250 ns
t
f
Fall time, drain output 200 ns
t
pd
Propagation delay time, SRCK↓ to SEROUT C
L
= 30 pF, I
D
= 48 mA 35 ns
T
or
SEROUT rise time (10% to 90%) C
L
= 30 pF 20 ns
T
of
SEROUT fall time (90% to 10%) C
L
= 30 pF 20 ns
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