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DS64MB201

www.ti.com

SNLS307E –JANUARY 2011–REVISED JULY 2013

DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and

De-Emphasis

Check for Samples: DS64MB201

FEATURES

DESCRIPTION

The DS64MB201 is a dual lane 2:1 multiplexer and

• Up to 6.4 Gbps dual lane 2:1 mux, 1:2 switch

1:2 switch or fan-out buffer with signal conditioning

or fan-out

suitable for SATA/SAS and other high-speed bus

• Adjustable receive equalization up to +33 dB

applications up to 6.4 Gbps. The device performs

gain

both receive equalization and transmit de-emphasis,

allowing maximum flexibility of physical placement

• Adjustable transmit de-emphasis up to −12 dB

within a system. The receiver's continuous time linear

• Adjustable transmit VOD

equalizer (CTLE) provides a boost of up to +33 dB at

• <0.25 UI of residual DJ at 6.4 Gbps with 40”

3 GHz and is capable of opening an input eye that is

FR4 trace

completely closed due to inter-symbol interference

(ISI) induced by the interconnect medium. The

• SATA/SAS: OOB signal pass-through

transmitter features a programmable output de-

• Adjustable electrical IDLE detect threshold

emphasis driver and allows amplitude voltage levels

• Low power

to be selected from 600 mVp-p to 1200 mVp-p to suit

• Signal conditioning programmable via pin multiple application scenarios. The signal conditioning

settings are programmable via control pin settings or

selection or SMBus interface

SMBus interface.

• Single 2.5V supply operation

To enable seamless upgrade from SAS/SATA 3.0

• >6 kV HBM ESD Rating

Gbps to 6.0 Gbps data rates without compromising

• 3.3V tolerant SMBus interface

physical reach, DS64MB201 automatically detects

• High speed signal flow–thru pinout package:

the incoming data rate and selects the optimal de-

54-pin WQFN (10 mm x 5.5 mm)

emphasis pulse width. The device detects the out-of-

band (OOB) idle and active signals of the SAS/SATA

specification and passes through with minimum signal

APPLICATIONS

distortion.

• SAS and SATA (1.5, 3.0 and 6 Gbps)

• XAUI (3.125 Gbps), RXAUI (6.25 Gbps)

• sRIO – Serial Rapid I/O

• Fibre Channel (4.25 Gbps)

• 10GBase-CX4, InfiniBand (SDR & DDR)

• FR-4 backplane traces

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS64MB201

SNLS307E –JANUARY 2011–REVISED JULY 2013

www.ti.com

Table 1. Pin Descriptions

Pin Name Pin Number I/O, Type

(1)

Pin Description

Differential High Speed I/O's

SIA0+, SIA0-, 45, 44, I, CML Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip

SIA1+, SIA1- 40, 39 50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD when

enabled.

SOA0+, SOA0-, 35, 34, O Inverting and non-inverting low power differential signaling 50Ω outputs with de-

SOA1+, SOA1- 31, 30 emphasis. Fully compatible with AC coupled CML inputs.

SIB0+, SIB0-, 43, 42, I, CML Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip

SIB1+, SIB1- 38, 37 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD when

enabled.

SOB0+, SOB0-, 33, 32, O Inverting and non-inverting low power differential signaling 50Ω outputs with de-

SOB1+, SOB1- 29, 28 emphasis. Fully compatible with AC coupled CML inputs.

DIN0+, DIN0-, 10, 11, I, CML Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip

DIN1+, DIN1- 15, 16 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD when

enabled.

DOUT0+, DOUT0-, 3, 4, O Inverting and non-inverting low power differential signaling 50Ω outputs with de-

DOUT1+, DOUT1- 7, 8 emphasis. Fully compatible with AC coupled CML inputs.

Control Pins — Shared (LVCMOS)

ENSMB 48 I, LVCMOS w/ System Management Bus (SMBus) enable pin.

internal pull- HIGH = Register Access: Provides access to internal digital registers to control

down such functions as equalization, de-emphasis, VOD, rate, channel powerdown, and

idle detection threshold.

LOW = Pin Mode: Access to the SMBus registers are disabled and control pins are

used to program VOD, rate, idle detection, equalization and de-emphasis settings.

Please refer to System Management Bus (SMBus) and Configuration Registers

section and Electrical Characteristics — Serial Management Bus Interface for

detailed information.

ENSMB = 1 (SMBUS MODE)

SDA, SCL 49, 50 I, LVCMOS ENSMB = 1

The SMBus SDA (data input/output bi-directional) and SCL (clock input) pins are

enabled.

AD[3:0] 54, 53, 47, 46 I, LVCMOS w/ ENSMB = 1

internal pull- SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus

down slave address inputs.

ENSMB = 0 (NORMAL PIN MODE)

EQA, 46, I, Float, EQA/B/D, 3–level input controls the level of equalization.

EQB, 49, LVCMOS EQA controls the level of equalization of the SIA0 and SIA1 inputs.

EQD 53 EQB controls the level of equalization of the SIB0 and SIB1 inputs.

EQD controls the level of equalization of the DIN0 and DIN1 inputs.

The pins are active only when ENSMB is de-asserted (Low).

When ENSMB goes high the SMBus control registers provide independent control

of each lane. See Table 2

DEMA, 47, I, Float, DEMA/B/D, 3–level input controls the level of de-emphasis.

DEMB, 50, LVCMOS DEMA controls the level of de-emphasis of the SOA0 and SOA1 outputs.

DEMD 54 DEMB controls the level of de-emphasis of the SOB0 and SOB1 outputs.

DEMD controls the level of de-emphasis of the DOUT0 and DOUT1 outputs.

The pins are active only when ENSMB is de-asserted (Low).

When ENSMB goes High the SMBus control registers provide independent control

of each lane. See Table 3

Control Pins — Both Modes (LVCMOS)

RATE 21 I, Float, RATE, 3–level input controls the pulse width of de-emphasis of the output.

LVCMOS RATE = 0 forces ~3 Gbps,

RATE = 1 forces ~6 Gbps,

RATE = Float enables auto rate detection. See Table 3

(1) 1 = HIGH, 0 = LOW, FLOAT = 3rd input state. FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-

up/pull-down. Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input. Input edge rate for

LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.

Product Folder Links: DS64MB201

DS64MB201

www.ti.com

SNLS307E –JANUARY 2011–REVISED JULY 2013

Table 1. Pin Descriptions (continued)

Pin Name Pin Number I/O, Type

(1)

Pin Description

TXIDLEDO 24 I, Float, TXIDLEDO, 3–level input controls the driver output.

LVCMOS TXIDLEDO = 0 disables the signal detect/squelch function for DOUT.

TXIDLEDO = 1 forces the DOUT to be muted (electrical idle).

TXIDLEDO = Float enables the signal auto detect/squelch function for DOUT and

the signal detect voltage threshold level can be adjusted using the SD_TH pin. See

Table 4

TXIDLESO 25 I, Float, TXIDLESO, 3–level input controls the driver output.

LVCMOS TXIDLESO = 0 disables the signal detect/squelch function for SOUT.

TXIDLESO = 1 forces the SOUT to be muted (electrical idle).

TXIDLESO = Float enables the signal auto detect/squelch function for SOUT and

the signal detect voltage threshold level can be adjusted using the SD_TH pin. See

Table 4

FANOUT 26 I, LVCMOS w/ FANOUT = 1 enables both A/B outputs for broadcast mode.

internal pull- FANOUT = 0 disables one of the outputs depending on the SEL0, SEL1 pin. See

down Table 6

SEL0, SEL1 19, 20 I, LVCMOS w/ SEL0 is for lane 0, SEL1 is for lane 1

internal pull- SEL0, SEL1 = 0 selects B input and B output.

down SEL0, SEL1 = 1 selects A input and A output. See Table 6

VOD0, VOD1 22, 23 I, LVCMOS w/ VOD[1:0] adjusts the output differential amplitude voltage level on all outputs.

internal pull- 00 set output VOD = 600 mVp-p (Default)

down 01 sets output VOD = 800 mVp-p

10 sets output VOD = 1000 mVp-p

11 sets output VOD = 1200 mVp-p

Note: VOD should be set to a minimum of 1000 mV to achieve stated DE levels.

Analog

SD_TH 27 I, ANALOG Threshold select pin for electrical idle detect threshold. Float pin for default 130

mVp-p (differential).

See Table 5

Power

VDD 9, 14, 36, 41, Power 2.5V Power supply pins.

GND DAP, 52 Power DAP is the large metal contact at the bottom side, located at the center of the 54

pin WQFN package. It should be connected to the GND plane with at least 4 via to

lower the ground impedance and improve the thermal performance of the package.

NOTE: DAP is the primary GND

NC 1, 2, 5, 6, 12, No Connect — Leave pin open

13, 17, 18

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: DS64MB201

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