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TI-DS90CP02.pdf
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TI-DS90CP02.pdf
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OUT0+
SEL0
OUT0-
OUT1+
OUT1-
SEL1
EN0
2:1 Mux2
2:1 Mux1
IN1-
IN1+
IN0-
IN0+
EN1
Control
Logic
DS90CP02
www.ti.com
SNLS267A –NOVEMBER 2008–REVISED MARCH 2013
DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch
Check for Samples: DS90CP02
1
FEATURES
DESCRIPTION
The DS90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint
2
• 1.5 Gbps per Channel
switch optimized for high-speed signal routing and
• Low Power: 70 mA in Dual Repeater Mode
switching over lossy FR-4 printed circuit board
@1.5 Gbps
backplanes and balanced cables. Fully differential
• Low Output Jitter
signal paths ensure exceptional signal integrity and
noise immunity. The non-blocking architecture allows
• Non-Blocking Architecture Allows 1:2 Splitter,
connections of any input to any output or outputs.
2:1 Mux, Crossover, and Dual Buffer
Configurations
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
• Flow-Through Pinout
the output levels are LVDS. A very small package
• LVDS/BLVDS/CML/LVPECL Inputs, LVDS
footprint requires a minimal space on the board while
Outputs
the flow-through pinout allows easy board layout. The
• Single 3.3V Supply
3.3V supply, CMOS process, and LVDS I/O ensure
high performance at low power over the entire
• Separate Control of Inputs and Outputs Allows
industrial -40 to +85°C temperature range.
for Power Savings
• Industrial -40 to +85°C Temperature Range
• 28-lead UQFN-28 Space Saving Package
Block Diagram
Figure 1. DS90CP02 Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
7 6 5 4 3 2 1
15 16 17 18 19 20 21
28
27
26
25
24
23
22
8
9
10
11
12
13
14
EN0
SEL0
SEL1
GND
GND
GND
GND
N/C
IN0+
IN0-
V
DDA
IN1+
IN1-
V
DD
EN1
V
DD
GND
V
DD
V
DD
N/C
GND
N/C
OUT0+
OUT0-
V
DDA
OUT1+
OUT1-
V
DD
DAP
(GND)
DS90CP02
SNLS267A –NOVEMBER 2008–REVISED MARCH 2013
www.ti.com
Table 1. PIN DESCRIPTIONS
Pin Pin
I/O, Type Description
Name Number
DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN0+ 9 I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
IN0− 10 compatible.
IN1+ 12 I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
IN1− 13 compatible.
SWITCHED DIFFERENTIAL OUTPUTS
OUT0+ 27 O, LVDS Inverting and non-inverting differential outputs. OUT0± can be connected to any one pair
OUT0− 26 IN0±, or IN1±. LVDS compatible .
OUT1+ 24 O, LVDS Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair
OUT1− 23 IN0±, or IN1±. LVDS compatible .
DIGITAL CONTROL INTERFACE
SEL0, SEL1 6 I, LVTTL Select Control Inputs
5
EN0, EN1 7 I, LVTTL Output Enable Inputs
15
N/C 8, 20, 28 Not Connected
POWER
V
DD
11, 14, 16, I, Power V
DD
= 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be connected from
18, 19, 22, V
DD
to GND plane.
25
GND DAP, 1, 2, I, Power Ground reference to LVDS and CMOS circuitry.
3, 4, 17, For the UQFN package, the DAP is used as the primary GND connection to the device.
21 The DAP is the exposed metal contact at the bottom of the UQFN-28 package. It should be
connected to the ground plane with at least 4 vias for optimal AC and thermal performance.
Connection Diagram
Figure 2. UQFN Top View
DAP = GND
See Package Number NJD0028A
2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90CP02
DS90CP02
www.ti.com
SNLS267A –NOVEMBER 2008–REVISED MARCH 2013
Configuration Select Truth Table
SEL0 SEL1 EN0 EN1 OUT0 OUT1 Mode
0 0 0 0 IN0 IN0 1:2 Splitter (IN1 powered down)
0 1 0 0 IN0 IN1 Dual Channel Repeater
1 0 0 0 IN1 IN0 Dual Channel Switch
1 1 0 0 IN1 IN1 1:2 Splitter (IN0 powered down)
0 1 0 1 IN0 PD Single Channel Repeater (Channel 1 powered down)
1 1 0 1 IN1 PD Single Channel Switch (IN0 and OUT1 powered down)
0 0 1 0 PD IN0 Single Channel Switch (IN1 and OUT0 powered down)
0 1 1 0 PD IN1 Single Channel Repeater (Channel 0 powered down)
X X 1 1 PD PD Both Channels in Power Down Mode
0 0 0 1 Invalid State*
1 0 0 1 Invalid State*
1 0 1 0 Invalid State*
1 1 1 0 Invalid State*
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS90CP02
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