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ASIC/FPGA

High Speed

I/O

Backplane/Cable

Sub-system

Switch Fabric Card

Line Card

OUT IN

DS64EV100

OUT IN

ASIC/FPGA

High Speed

I/O

DS64EV100

www.ti.com

SNLS232E –OCTOBER 2006–REVISED FEBRUARY 2013

DS64EV100 Programmable Single Equalizer

Check for Samples: DS64EV100

FEATURES

DESCRIPTION

The DS64EV100 programmable equalizer provides

• Equalizes up to 24 dB loss at 10 Gbps

compensation for transmission medium losses and

• Equalizes up to 22 dB loss at 6.4 Gbps

reduces the medium-induced deterministic jitter for

• 8 levels of programmable equalization

NRZ data channel. The DS64EV100 is optimized for

operation up to 10 Gbps for both cables and FR4

• Operates up to 10 Gbps with 30” FR4 traces

traces. The equalizer channel has eight levels of

• Operates up to 6.4 Gbps with 40” FR4 traces

input equalization that can be programmed by three

• 0.175 UI residual deterministic jitter at 6.4

control pins.

Gbps with 40” FR4 traces

The equalizer supports both AC and DC-coupled data

• Single 2.5V or 3.3V power supply

paths for long run length data patterns such as

• Supports AC or DC-Coupling with wide input

PRBS-31, and balanced codes such as 8b/10b. The

device uses differential current-mode logic (CML)

common-mode

inputs and outputs. The DS64EV100 is available in a

• Low power consumption: 100 mW Typ at 2.5V

3 mm x 4 mm 14-pin leadless WSON package.

• Small 3 mm x 4 mm 14-pin WSON package

Power is supplied from either a 2.5V or 3.3V supply.

• > 8 kV HBM ESD Rating

• -40 to 85°C operating temperature range

Simplified Application Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS64EV100

www.ti.com

SNLS232E –OCTOBER 2006–REVISED FEBRUARY 2013

Absolute Maximum Ratings

(1)(2)

Supply Voltage (V

) −0.5V to +4V

CMOS Input Voltage −0.5V to +4.0V

CMOS Output Voltage −0.5V to +4.0V

CML Input/Output Voltage −0.5V to +4.0V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Lead Temperature

Soldering, 4 sec +260°C

ESD Rating

HBM, 1.5 kΩ, 100 pF > 8 kV

EIAJ, 0Ω, 200 pF > 250 V

Thermal Resistance, θ

No Airflow 40 °C/W

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute

Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating

Voltages only.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for

availability and specifications.

Recommended Operating Conditions

MIN TYP MAX UNIT

Supply Voltage

(1)

DD2.5

to GND 2.375 2.5 2.625 V

DD3.3

to GND 3.0 3.3 3.6 V

Ambient Temperature −40 25 +85 °C

(1) The V

DD2.5

is V

= 2.5V ± 5% and V

DD3.3

is V

= 3.3V ± 10%.

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

POWER

DD3.3

140 200 mW

Power Supply

Consumption

DD2.5

100 150 mW

50 Hz – 100 Hz 100 mV

P-P

Supply Noise Tolerance

N 100 Hz – 10 MHz 40 mV

P-P

(3)

10 MHz – 1.6 GHz 10 mV

P-P

LVTTL DC SPECIFICATIONS

DD2.

DD2.5

1.6 V

High Level Input Voltage

DD3.

2.0 V

Low Level Input Voltage −0.3 0.8 V

= –3 mA, V

DD3.3

2.4 V

High Level Input Voltage

2.0 V

Low Level Input Voltage I

= 3 mA 0.4 V

(1) Typical values represent most likely parametric norms at V

= 3.3V or 2.5V, T

= 25°C., and at the Recommended Operation

Conditions at the time of product characterization and are not guaranteed.

(2) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not guaranteed.

(3) Allowed supply noise (mV

P-P

sine wave) under typical conditions.

Product Folder Links: DS64EV100

DS64EV100

SNLS232E –OCTOBER 2006–REVISED FEBRUARY 2013

www.ti.com

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless other specified.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

POWER

= V

+1.8 +15 µA

Input Current

= GND −15 0 µA

Input Leakage Current V

= GND, with internal pull-down resistors +95 µA

IN-P

with Internal Pull-

= GND, with internal pull-up resistors –20 µA

Down/Up Resistors

CML RECEIVER INPUTS (IN+, IN−)

AC-Coupled or DC-Coupled Requirement, Differential

Source Transmit Launch

measurement at point A. 400 1600 mV

P-P

Signal Level (IN diff)

Figure 1

Differential measurement at point B .

INTRE

Input Threshold Voltage 120 mV

P-P

Figure 1

Supply Voltage of

DDTX

DC-Coupled Requirement 1.6 V

Transmitter to EQ

DC-Coupled Requirement Differential measurement at

Input Common-Mode V

DDT

ICMDC

point A. V

DDTX

-0.8 V

Voltage

-0.2

Figure 1

(4)

Differential Input Return

100 MHz – 3.2 GHz, with fixture’s effect de-embedded 10 dB

Loss

Input Resistance Differential Across IN+ and IN-. Figure 4 85 100 115 Ω

CML OUTPUTS (OUT+, OUT−)

Differential measurement with OUT+ and OUT-

Output Differential

terminated by 50Ω to GND, AC-Coupled 550 620 725 mV

P-P

Voltage Level (OUT diff)

Figure 2

Single-ended measurement DC-Coupled with 50Ω

Output Common-Mode V

OCM

terminations V

-0.2 V

Voltage 0.1

(5)

20% to 80% of differential output voltage, measured

within 1” from output pins.

, t

Transition Time 20 60 ps

Figure 2

(5)

Output Resistance Single-ended to V

42 50 58 Ω

Differential Output 100 MHz – 1.6 GHz, with fixture’s effect de-

10 dB

Return Loss embedded. IN+ = static high.

Differential Low to High Propagation delay measurement at 50% V

between

PLHD

240 ps

Propagation Delay input to output, 100 Mbps

Figure 3

(5)

Differential High to Low

PHLD

240 ps

Propagation Delay

EQUALIZATION

30” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7

Residual Deterministic

DJ1 (2

-1) pattern 0.20 UI

P-P

Jitter at 10 Gbps

(6)(7)

40” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7

Residual Deterministic

DJ2 (2

-1) pattern 0.17 0.26 UI

P-P

Jitter at 6.4 Gbps

(6)(7)

40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7

Residual Deterministic

DJ3 (2

-1) pattern 0.12 0.20 UI

P-P

Jitter at 5 Gbps

(6)(7)

40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7

Residual Deterministic

DJ4 (2

-1) pattern 0.10 0.16 UI

P-P

Jitter at 2.5 Gbps

(6)(7)

(4) Measured with clock-like {11111 00000} pattern.

(5) Measured with clock-like {11111 00000} pattern.

(6) Specification is guaranteed by characterization at optimal boost setting and is not tested in production.

(7) Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point

A of Figure 1). Random jitter is removed through the use of averaging or similar means.

Product Folder Links: DS64EV100

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