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ASIC/FPGA

High Speed I/O

Backplane/Cable

Sub-system

Switch Fabric Card

Line Card

OUT

DS64EV400

OUT IN

ASIC/FPGA

High Speed I/O

DS64EV400

www.ti.com

SNLS281H –AUGUST 2007–REVISED APRIL 2013

DS64EV400 Programmable Quad Equalizer

Check for Samples: DS64EV400

FEATURES

DESCRIPTION

The DS64EV400 programmable quad equalizer

• Equalizes up to 24 dB Loss at 10 Gbps

provides compensation for transmission medium

• Equalizes up to 22 dB Loss at 6.4 Gbps

losses and reduces the medium-induced deterministic

• 8 Levels of Programmable Equalization

jitter for four NRZ data channels. The DS64EV400 is

optimized for operation up to 10 Gbps for both cables

• Settable through Control Pins or SMBus

and FR4 traces. Each equalizer channel has eight

Tnterface

levels of input equalization that can be programmed

• Operates up to 10 Gbps with 30” FR4 Traces

by three control pins, or individually through a Serial

• Operates up to 6.4 Gbps with 40” FR4 Traces

Management Bus (SMBus) interface.

• 0.175 UI Residual Deterministic Jitter at 6.4

The equalizer supports both AC and DC-coupled data

Gbps with 40” FR4 Traces

paths for long run length data patterns such as

PRBS-31, and balanced codes such as 8b/10b. The

• Single 2.5V or 3.3V Power Supply

device uses differential current-mode logic (CML)

• Signal Detect for Individual Channels

inputs and outputs. The DS64EV400 is available in a

• Standby Mode for Individual Channels

7 mm x 7 mm 48-pin leadless WQFN package.

• Supports AC or DC-Coupling with Wide Input

Power is supplied from either a 2.5V or 3.3V supply.

Common-Mode

• Low Power Consumption: 375 mW Typ at 2.5V

• Small 7 mm x 7 mm 48-Pin WQFN Package

• 9 kV HBM ESD Rating

• -40 to 85°C Operating Temperature Range

Simplified Application Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013

www.ti.com

Pin Descriptions

Pin Name Pin No. I/O, Type

(1)

Description

HIGH SPEED DIFFERENTIAL I/O

IN_0+ 1 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

IN_0– 2 terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 7.

IN_1+ 4 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

IN_1– 5 terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 7.

IN_2+ 8 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

IN_2– 9 terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 7.

IN_3+ 11 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

IN_3– 12 terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 7.

OUT_0+ 36 O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω

OUT_0– 35 terminating resistor connects OUT_0+ to V

and OUT_0- to V

OUT_1+ 33 O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω

OUT_1– 32 terminating resistor connects OUT_1+ to V

and OUT_1- to V

OUT_2+ 29 O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω

OUT_2– 28 terminating resistor connects OUT_2+ to V

and OUT_2- to V

OUT_3+ 26 O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω

OUT_3– 25 terminating resistor connects OUT_3+ to V

and OUT_3- to V

EQUALIZATION CONTROL

BST_2 37 I, LVCMOS BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is

BST_1 14 internally pulled high. BST_1 and BST_0 are internally pulled low.

BST_0 23

DEVICE CONTROL

EN0 44 I, LVCMOS Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

EN1 42 I, LVCMOS Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

EN2 40 I, LVCMOS Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

EN3 38 I, LVCMOS Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

FEB 21 I, LVCMOS Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]

pins. When held low, the equalizer boost setting is controlled by SMBus (Table 1) register bits.

FEB is internally pulled High.

SD0 45 O, LVCMOS Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.

SD1 43 O, LVCMOS Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.

SD2 41 O, LVCMOS Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.

SD3 39 O, LVCMOS Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.

POWER

3, 6, 7, Power V

= 2.5V ± 5% or 3.3V ± 10%. V

pins should be tied to V

plane through low inductance

10, 13, path. A 0.01μF bypass capacitor should be connected between each V

pin to GND planes.

15, 46

GND 22, 24, Power Ground reference. GND should be tied to a solid ground plane through a low impedance path.

27, 30,

31, 34

DAP PAD Power Ground reference. The exposed pad at the center of the package must be connected to ground

plane of the board.

SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS

SDA 18 I/O, LVCMOS Data input/output (bi-directional). Internally pulled high.

SDC 17 I, LVCMOS Clock input. Internally pulled high.

CS 16 I, LVCMOS Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When

pulled low, access to the equalizer SMBus registers are disabled. Please refer to “ SMBus

configuration Registers” section for detail information.

Other

Reserv 19, 20 Reserved. Do not connect.

47,48

(1) Note: I = Input O = Output

Product Folder Links: DS64EV400

DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013

www.ti.com

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage V

DD2.5

to GND 2.375 2.5 2.625 V

DD3.3

to GND 3.0 3.3 3.6 V

Ambient Temperature −40 25 +85 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless other specified.

Parameter Test Conditions Min Typ

(1)

Max Units

POWER

P Power Supply Consumption Device Output Enabled

490 700 mW

(EN [0–3] = High), V

DD3.3

(2)

Device Output Disable

100 mW

(EN [0–3] = Low), V

DD3.3

P Power Supply Consumption Device Output Enabled

360 490 mW

(EN [0–3] = High), V

DD2.5

(2)

Device Output Disable

(EN [0–3] = Low), V

DD2.5

(2)

N Supply Noise Tolerance

(3)

50 Hz — 100 Hz 100 mV

P-P

100 Hz — 10 MHz 40 mV

P-P

10 MHz — 1.6 GHz 10 mV

P-P

LVCMOS DC SPECIFICATIONS

High Level Input Voltage V

DD3.3

2.0 V

DD3.3

DD2.5

1.6 V

DD2.5

Low Level Input Voltage -0.3 0.8 V

High Level Output Voltage I

= -3mA, V

DD3.3

2.4 V

= -3mA, V

DD2.5

2.0

Low Level Output Voltage I

= 3mA 0.4 V

Input Leakage Current V

= V

+15 μA

= GND -15 μA

IN-P

Input Leakage Current with Internal V

= V

, with internal pull-down resistors +120 μA

Pull-Down/Up Resistors

= GND, with internal pull-up resistors -20 μA

SIGNAL DETECT

SDH Signal Detect ON Threshold Level Default input signal level to assert SD pin, 6.4 70 mV

p-p

Gbps

SDI Signal Detect OFF Threshold Level Default input signal level to de-assert SD, 6.4 40 mV

p-p

Gbps

CML RECEIVER INPUTS (IN_n+, IN_n-)

Source Transmit Launch Signal Level AC-Coupled or DC-Coupled Requirement,

(IN diff) Differential measurement at point A. 400 1600 mV

P-P

Figure 2

INTRE

Input Threshold Voltage Differential measurement at

120 mV

P-P

point B. Figure 2

DDTX

Supply Voltage of Transmitter to EQ DC-Coupled Requirement

(4)

1.6 V

ICMDC

Input Common Mode Voltage DC-Coupled Requirement, Differential V

DDTX

– V

DDTX

measurement at point A. Figure 2,

(5)

0.8 – 0.2

Differential Input Return Loss 100 MHz – 3.2 GHz, with fixture’s effect de-

10 dB

embedded

(1) Typical values represent most likely parametric norms at V

= 3.3V or 2.5V, T

= 25°C, and at the Recommended Operation

Conditions at the time of product characterization and are not ensured.

(2) The V

DD2.5

is V

= 2.5V ± 5% and V

DD3.3

is V

= 3.3V ± 10%.

(3) Allowed supply noise (mV

P-P

sine wave) under typical conditions.

(4) Recommended value. Parameter not tested in production.

(5) Measured with clock-like {11111 00000} pattern.

Product Folder Links: DS64EV400

DS64EV400

www.ti.com

SNLS281H –AUGUST 2007–REVISED APRIL 2013

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges with default register settings unless other specified.

Parameter Test Conditions Min Typ

(1)

Max Units

Input Resistance Differential across IN+ and IN-, Figure 7 85 100 115 Ω

CML OUTPUTS (OUT_n+, OUT_n-)

Output Differential Voltage Level Differential measurement with OUT+ and OUT-

(OUT diff) terminated by 50Ω to GND, AC-Coupled 500 620 725 mV

P-P

Figure 3

OCM

Output Common Mode Voltage Single-ended measurement DC-Coupled with V

– V

–

50Ω terminations

(5)

0.2 0.1

, t

Transition Time 20% to 80% of differential output voltage,

measured within 1” from output pins. 20 60 ps

Figure 3,

(5)

Output Resistance Single ended to V

42 50 58 Ω

Differential Output Return Loss 100 MHz – 1.6 GHz, with fixture’s effect de-

10 dB

embedded. IN+ = static high.

PLHD

Differential Low to High Propagation Propagation delay measurement at 50% VO

240 ps

Delay between input to output, 100 Mbps. Figure 4,

(5)

PHLD

Differential High to Low Propagation

240 ps

Delay

CCSK

Inter Pair Channel to Channel Skew Difference in 50% crossing between channels 7 ps

PPSK

Part to Part Output Skew Difference in 50% crossing between outputs 20 ps

EQUALIZATION

DJ1 Residual Deterministic Jitter 30” of 6 mil microstrip FR4,

0.20 UI

P-P

at 10 Gbps EQ Setting 0x06, PRBS-7 (2

-1) pattern.

(6)

DJ2 Residual Deterministic Jitter 40” of 6 mil microstrip FR4,

0.17 0.26 UI

P-P

at 6.4 Gbps EQ Setting 0x06, PRBS-7 (2

-1) pattern.

(7)(6)

DJ3 Residual Deterministic Jitter 40” of 6 mil microstrip FR4,

0.12 0.20 UI

P-P

at 5 Gbps EQ Setting 0x07, PRBS-7 (2

-1) pattern.

(7) (6)

DJ4 Residual Deterministic Jitter 40” of 6 mil microstrip FR4,

0.1 0.16 UI

P-P

at 2.5 Gbps EQ Setting 0x07, PRBS-7 (2

-1) pattern.

(7)(6)

RJ Random Jitter See

(8)(9)

0.5 psrms

SIGNAL DETECT and ENABLE TIMING

ZISD

Input OFF to ON detect — SD Output Response time measurement at V

to SD

35 ns

High Response Time output, V

= 800 mV

P-P

, 100 Mbps, 40” of 6 mil

microstrip FR4

IZSD

Input ON to OFF detect — SD Output

400 ns

Figure 2 and Figure 5,

(8)

Low Response Time

OZOED

EN High to Output ON Response Response time measurement at EN input to

150 ns

Time V

, V

= 800 mV

P-P

, 100 Mbps, 40” of 6 mil

microstrip FR4

ZOED

EN Low to Output OFF Response

5 ns

Figure 2 and Figure 7,

(8)

Time

(6) Deterministic jitter is measured at the differential outputs (point C of Figure 2), minus the deterministic jitter before the test channel (point

A of Figure 2). Random jitter is removed through the use of averaging or similar means.

(7) Specification is ensured by characterization at optimal boost setting and is not tested in production.

(8) Measured with clock-like {11111 00000} pattern.

(9) Random jitter contributed by the equalizer is defined as sqrt (J

OUT

– J

). J

OUT

is the random jitter at equalizer outputs in ps-rms, see

point C of Figure 2; J

is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 2.

Product Folder Links: DS64EV400

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