TI-DS90CP04.pdf资源-CSDN文库

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IN1+

IN1-

IN2+

IN2-

IN3+

IN3-

IN4+

IN4-

OUT1+

OUT1-

OUT2+

OUT2-

OUT3+

OUT3-

OUT4+

OUT4-

SCLK

SI/SEL1

CSO

CSCLK

EN1 EN2 EN3 EN4

4:1 MUX1

4:1 MUX2 4:1 MUX3

4:1 MUX4

LOAD

MODE

Digital Control

Interface

RSO

RSCLK

SEL0

DS90CP04

www.ti.com

SNLS154I –JANUARY 2002–REVISED APRIL 2013

DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch

Check for Samples: DS90CP04

FEATURES

DESCRIPTION

DS90CP04 is a 4x4 digital cross-point switch with

• DC - 1.5 Gbps Low Jitter, Low Skew Operation

broadside input and output pins for efficient board

• Pin and Serial Interface Configurable, Fully

layout. It utilizes Low Voltage Differential Swing

Differential, Non-blocking Architecture

(LVDS) technology for low power, high-speed

• Wide Input Common Mode Voltage Range

operation. Data paths are fully differential from input

to output for low noise. The non-blocking architecture

Enables Easy Interface to LVDS/LVPECL/2.5V-

allows connections of any input to any output or

CML Drivers

outputs. The switch matrix consists of four differential

• TRI-STATE LVDS Outputs

4:1 multiplexes. Each output channel connects to one

• Serial Control Interface with Read-back

of the four inputs common to all multiplexers.

Capability

A simple serial control interface or a configuration

• Double Register Loading

select port is activated by the state of the MODE pin.

• Single +2.5V Supply

When utilizing the serial control interface a single

load command will update the new switch

• Small 6x6 mm WQFN-32 Space Saving

configuration for all outputs simultaneously.

Package

• Fabricated with Advanced CMOS Process

Technology

Functional Block Diagrams

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90CP04

SNLS154I –JANUARY 2002–REVISED APRIL 2013

www.ti.com

PIN DESCRIPTIONS (continued)

Pin Pin

I/O, Type Description

Name Number

DIGITAL CONTROL INTERFACE

SCLK 6 I, LVCMOS Control clock to latch in programming data at SI. SCLK can be 0 MHz to 100 MHz. SCLK

should be burst of clock pulses active only while accessing the device. After completion of

programming, SCLK should be kept at logic low to minimize potential noise injection into

the high-speed differential data paths.

SI / SEL1 7 I, LVCMOS Programming data to select the switch configuration. Data is latched into the input buffer

SEL0 5 I, LVCMOS Programming data to select the switch configuration.

CSO 18 O, LVCMOS With MODE low, control data is shifted out at CSO (RSO) for cascading to the next device

RSO 2 in the serial chain. The control data at CSO (RSO) is identical to that shifted in at SI with

the exception of the device column (row) address being decremented by one internally

before propagating to the next device in the chain. CSO (RSO) is clocked out at the rising

edge of SCLK.

CSCLK 19 O, LVCMOS With MODE low, these pins function as a buffered control clock from SCLK. CSCLK

RSCLK 3 (RSCLK) is used for cascading the serial control bus to the next device in the serial chain.

LOAD 22 I, LVCMOS When LOAD is high and SCLK makes a LH transition, the device transfers the

programming data in the load register into the configuration registers. The new switch

configuration for all outputs takes effect. LOAD needs to remain high for only one SCLK

cycle to complete the process, holding LOAD high longer repeats the transfer to the

configuration register.

MODE 23 I, LVCMOS When MODE is low, the SCLK is active and a buffered SCLK signal is present at the

CLKOUT output. When MODE is high, the SCLK signal is uncoupled from register and

state machine internals. Internal registers will see an active low signal until MODE is

brought Low again.

POWER

1, 8, 17, I, Power V

= 2.5V ±5%. At least 4 low ESR 0.01 µF bypass capacitors should be connected from

24 V

to GND plane.

GND 4, 20, 21, I, Power Ground reference to LVDS and CMOS circuitry.

DAP DAP is the exposed metal contact at the bottom of the WQFN-32 package. The DAP is

used as the primary GND connection to the device. It should be connected to the ground

plane with at least 4 vias for optimal AC and thermal performance.

Serial Interface Truth Table

LOAD MODE SCLK Resulting Action

0 0 LH The current state on SI is clocked into the input shift register.

0 1 LH Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and

CSCLK outputs will drive an active Low signal until MODE is brought Low again. See

Configuration Select Truth Table below.

LH 0 X Loads OUT1–OUT4 configuration information from last valid frame. Places contents of load

from the SCLK input.

1 1 LH Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and

CSCLK outputs will drive an active Low signal until MODE is brought Low again. See

Configuration Select Truth Table below.

Configuration Select Truth Table

MODE SEL1 SEL0 Resulting Action

0 X X The SEL0/1 pins only function in configuration select mode. See below.

1 0 0 Distribution: IN1 - OUT1 OUT2 OUT3 OUT4

1 0 1 Distribution: IN2 - OUT1 OUT2 OUT3 OUT4

1 1 0 Redundancy: IN1 - OUT1 OUT2 and IN3 - OUT3 OUT4

1 1 1 Broadside: IN1 - OUT1, IN2 - OUT2, IN3 - OUT3, IN4 - OUT4

Product Folder Links: DS90CP04

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