TI-DS90CF388.pdf_LVDS800x600时钟资源-CSDN文库

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TI的DS90C387和DS90CF388是专为FPD-Link（Flat Panel Display Link）接口设计的双像素LVDS显示接口（LDI）发射器和接收器。这两个器件主要用于在主机和平板显示器之间传输双像素数据，最高支持QXGA分辨率，即2048x1536像素。以下是对这两个器件主要特性和功能的详细解释： 1. **兼容性与规格**：DS90C387和DS90CF388遵循OpenLDI（开放的数字显示接口）规范，适用于数字显示接口。它们可以支持从SVGA（800x600）到QXGA的各种面板分辨率。 2. **时钟支持**：DS90C387支持32.5到112MHz的时钟频率，而DS90CF388则支持40到112MHz的时钟频率。此外，DS90CF388还有一个模式，可以处理高达170MHz的单像素时钟输入。 3. **数据速率**：在最大112MHz的双像素率下，LVDS数据线速度达到672Mbps，总带宽可达5.38Gbps，即每秒672兆字节的数据传输量。 4. **信号控制**：除了48位（双像素24位色）CMOS/TTL数据转换为8个LVDS数据流外，DS90C387/DS90CF388还会在消隐期间发送控制信号，如垂直同步（VSYNC）、水平同步（HSYNC）、数据使能（DE）以及两个用户自定义信号。 5. **增强功能**： - **预加重**：减少电缆负载效应，提高信号质量。 - **直流平衡数据传输**：由发射器提供，减少因ISI（ intersymbol interference，符号间干扰）引起的失真。 - **电缆时钟偏移校正**：允许+/−1 LVDS数据位时间（最高达80MHz时钟率）的对对时钟偏移校正，同时具有对内对 skew 的容忍度为300ps。 - **双像素架构**：支持与图形用户界面（GUI）和时序控制器的接口，可选单像素发射器输入支持单像素GUI接口。 6. **互操作性**：第三个模式提供了与FPD-Link设备的互操作性，确保了与不同系统的兼容性。 7. **性能提升**：相比前代FPD-Link设备，这些LDI芯片组在三个方面进行了增强，以提高带宽、支持更高的时钟频率和更长的电缆驱动距离： - **增加带宽**：最大像素时钟率提高至112（170）MHz。 - **电缆驱动能力**：通过提供8个串行LVDS输出来增强电缆驱动能力。 - **抗噪声能力**：发射器能够抵抗噪声干扰，确保数据传输的稳定性。 DS90C387和DS90CF388是高性能的FPD-Link解决方案，用于高分辨率视频传输，它们优化了数据传输效率，支持长距离低成本电缆，并具有强大的兼容性和互操作性。

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DS90C387, DS90CF388

www.ti.com

SNLS012H –MAY 2000–REVISED APRIL 2013

DS90C387, DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

Check for Samples: DS90C387, DS90CF388

FEATURES

DESCRIPTION

The DS90C387/DS90CF388 transmitter/receiver pair

• Complies with OpenLDI Specification for

is designed to support dual pixel data transmission

Digital Display Interfaces

between Host and Flat Panel Display up to QXGA

• 32.5 to 112/170MHz Clock Support for

resolutions. The transmitter converts 48 bits (Dual

DS90C387, 40 to 112MHz Clock Support for

Pixel 24-bit color) of CMOS/TTL data into 8 LVDS

DS90CF388

(Low Voltage Differential Signalling) data streams.

Control signals (VSYNC, HSYNC, DE and two user-

• Supports SVGA through QXGA Panel

defined signals) are sent during blanking intervals. At

Resolutions

a maximum dual pixel rate of 112MHz, LVDS data

• Drives Long, Low Cost Cables

line speed is 672Mbps, providing a total throughput of

• Up to 5.38Gbps Bandwidth

5.38Gbps (672 Megabytes per second). Two other

modes are also supported. 24-bit color data (single

• Pre-Emphasis Reduces Cable Loading Effects

pixel) can be clocked into the transmitter at a

• DC Balance Data Transmission Provided by

maximum rate of 170MHz. In this mode, the

Transmitter Reduces ISI Distortion

transmitter provides single-to-dual pixel conversion,

• Cable Deskew of +/−1 LVDS Data Bit Time (up

and the output LVDS clock rate is 85MHz maximum.

to 80 MHz Clock Rate) of Pair-to-Pair Skew at

The third mode provides inter-operability with FPD-

Link devices.

Receiver Inputs; Intra-Pair Skew Tolerance of

300ps

The LDI chipset is improved over prior generations of

• Dual Pixel Architecture Supports Interface to

FPD-Link devices and offers higher bandwidth

GUI and Timing Controller; Optional Single support and longer cable drive with three areas of

enhancement. To increase bandwidth, the maximum

Pixel Transmitter Inputs Support Single Pixel

pixel clock rate is increased to 112 (170) MHz and 8

GUI Interface

serialized LVDS outputs are provided. Cable drive is

• Transmitter Rejects Cycle-to-Cycle Jitter

enhanced with a user selectable pre-emphasis

• 5V Tolerant on Data and Control Input Pins

feature that provides additional output current during

transitions to counteract cable loading effects. DC

• Programmable Transmitter Data and Control

balancing on a cycle-to-cycle basis, is also provided

Strobe Select (Rising or Falling Edge Strobe)

to reduce ISI (Inter-Symbol Interference). With pre-

• Backward Compatible Configuration Select

emphasis and DC balancing, a low distortion eye-

with FPD-Link

pattern is provided at the receiver end of the cable. A

• Optional Second LVDS Clock for Backward

cable deskew capability has been added to deskew

Compatibility w/ FPD-Link long cables of pair-to-pair skew of up to +/−1 LVDS

data bit time (up to 80 MHz Clock Rate). These three

• Support for Two Additional User-Defined

enhancements allow cables 5+ meters in length to be

Control Signals in DC Balanced Mode

driven. This chipset is an ideal means to solve EMI

• Compatible with ANSI/TIA/EIA-644-1995 LVDS

and cable size problems for high-resolution flat panel

Standard

applications. It provides a reliable interface based on

LVDS technology that delivers the bandwidth needed

for high-resolution panels while maximizing bit times,

and keeping clock rates low to reduce EMI and

shielding requirements. For more details, please refer

to Applications Information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90C387, DS90CF388

www.ti.com

SNLS012H –MAY 2000–REVISED APRIL 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)(2)

Supply Voltage (V

) −0.3V to +4V

CMOS/TTL Input Voltage −0.3V to +5.5V

CMOS/TTL Output Voltage −0.3V to (V

+ 0.3V)

LVDS Receiver Input Voltage −0.3V to +3.6V

LVDS Driver Output Voltage −0.3V to +3.6V

LVDS Output Short Circuit Duration Continuous

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Lead Temperature (Soldering, 4 seconds) +260°C

DS90C387 2.8W

Maximum Package Power Dissipation Capacity at 25°C, 100 TQFP

Package

DS90CF388 2.8W

DS90C387 18.2mW/°C above +25°C

Package Derating

DS90CF388 18.2mW/°C above +25°C

HBM, 1.5kΩ, 100pF > 6 kV

DS90C387

EIAJ, 0Ω, 200pF > 300 V

ESD Rating

HBM, 1.5kΩ, 100pF > 2 kV

DS90CF388

EIAJ, 0Ω, 200pF > 200 V

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply

that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

Recommended Operating Conditions

Min Nom Max Unit

Supply Voltage (V

) 3.0 3.3 3.6 V

Operating Free Air Temperature (T

−10 +25 +70 °C

Receiver Input Range 0 2.4 V

Supply Noise Voltage (V

) 100 mV

p-p

Electrical Characteristics

(1)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

CMOS/TTL DC SPECIFICATIONS (Tx inputs, Rx outputs, control inputs and outputs)

High Level Input Voltage 2.0 5.0 V

Low Level Input Voltage GND 0.8 V

High Level Output Voltage I

= −0.4 mA 2.7 2.9 V

= −2 mA 2.7 2.85 V

Low Level Output Voltage I

= 2 mA 0.1 0.3 V

Input Clamp Voltage I

= −18 mA −0.79 −1.5 V

Input Current V

= 0.4V, 2.5V or V

+1.8 +15 µA

= GND −15 0 µA

Output Short Circuit Current V

OUT

= 0V −120 mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

unless otherwise specified (except V

and ΔV

Product Folder Links: DS90C387 DS90CF388

DS90C387, DS90CF388

www.ti.com

SNLS012H –MAY 2000–REVISED APRIL 2013

Electrical Characteristics

(1)

(continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

RECEIVER SUPPLY CURRENT

ICCRW Receiver Supply Current, C

= 8 pF, f = 40MHz 125 160 mA

Worst Case Worst Case Pattern

f = 65 MHz 200 250 mA

(Figure 1 and Figure 4),

f = 85 MHz 240 275 mA

DUAL (48-bit RGB),

BAL=High (enabled)

f = 112 MHz 250 300 mA

ICCRG Receiver Support Current, C

= 8 pF, f = 40MHz 60 95 mA

16 Grayscale 16 Grayscale Pattern

f = 65 MHz 95 125 mA

(Figure 2 and Figure 4),

f = 85 MHz 115 150 mA

DUAL (48-bit RGB),

BAL=High (enabled)

f = 112 MHz 150 270 mA

ICCRZ Receiver Supply Current, PD = Low 255 300 µA

Power Down Receiver Outputs stay low during Powerdown

mode

Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Unit

TCIT TxCLK IN Transition Time (Figure 5) DUAL=Gnd or Vcc 1.0 2.0 3.0 ns

DUAL=1/2Vcc 1.0 1.5 1.7 ns

TCIP TxCLK IN Period (Figure 6) DUAL=Gnd or Vcc 8.928 T 30.77 ns

DUAL=1/2Vcc 5.88 15.38 ns

TCIH TxCLK in High Time (Figure 6) 0.35T 0.5T 0.65T ns

TCIL TxCLK in Low Time (Figure 6) 0.35T 0.5T 0.65T ns

TXIT TxIN Transition Time 1.5 6.0 ns

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Unit

LLHT LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V (disabled) 0.14 0.7 ns

LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.6 ns

LHLT LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V (disabled) 0.16 0.8 ns

LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.7 ns

TBIT Transmitter Output Bit Width DUAL=Gnd or Vcc 1/7 TCIP ns

DUAL=1/2Vcc 2/7 TCIP ns

TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70 MHz −250 0 +250 ps

f = 70 to 112 MHz −200 0 +200 ps

TCCS TxOUT Channel to Channel Skew 100 ps

TSTC TxIN Setup to TxCLK IN (Figure 6) 2.7 ns

THTC TxIN Hold to TxCLK IN (Figure 6) 0 ns

TJCC Transmitter Jitter Cycle-to-cycle (Figure 14 and f = 112 MHz 85 100 ps

Figure 15) , DUAL=Vcc

(1)

f = 85 MHz 60 75 ps

f = 65 MHz 70 80 ps

f = 56 MHz 100 120 ps

f = 32.5 MHz 75 110 ps

TPLLS Transmitter Phase Lock Loop Set (Figure 8) 10 ms

(1) The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is

measured with a cycle-to-cycle jitter of ±3ns applied to the input clock signal while data inputs are switching (see Figure 14 and

Figure 15). A jitter event of 3ns, represents worse case jump in the clock edge from most graphics VGA chips currently available. This

parameter is used when calculating system margin as described in AN-1059 (SNLA050).

Product Folder Links: DS90C387 DS90CF388

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