TI-DS90CF564.pdf资源-CSDN文库

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DS90CF563, DS90CF564

www.ti.com

SNLS107E –JULY 1997–REVISED APRIL 2013

DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link - 65 MHz

Check for Samples: DS90CF563, DS90CF564

FEATURES

DESCRIPTION

The DS90CF563 transmitter converts 21 bits of

• 20 to 65 MHz Shift Clk Support

CMOS/TTL data into three LVDS (Low Voltage

• Up to 171 Mbytes/s Bandwidth

Differential Signaling) data streams. A phase-locked

• Cable Size is Reduced to Save Cost

transmit clock is transmitted in parallel with the data

streams over a fourth LVDS link. Every cycle of the

• 290 mV Swing LVDS Devices for Low EMI

transmit clock 21 bits of input data are sampled and

• Low Power CMOS Design (< 550 mW typ)

transmitted. The DS90CF564 receiver converts the

• Power-down Mode Saves Power (< 0.25 mW)

LVDS data streams back into 21 bits of CMOS/TTL

data. At a transmit clock frequency of 65 MHz, 18 bits

• PLL Requires No External Components

of RGB data and 3 bits of LCD timing and control

• Low Profile 48-Lead TSSOP Package

data (FPLINE, FPFRAME, DRDY) are transmitted at

• Falling Edge Data Strobe

a rate of 455 Mbps per LVDS data channel. Using a

65 MHz clock, the data throughput is 171 Mbytes per

• Compatible with TIA/EIA-644 LVDS Standard

second. These devices are offered with falling edge

• Single Pixel Per Clock XGA (1024 x 768)

data strobes for convenient interface with a variety of

• Supports VGA, SVGA, XGA and Higher

graphics and LCD panel controllers.

• 1.3 Gbps Throughput

This chipset is an ideal means to solve EMI and

cable size problems associated with wide, high speed

TTL interfaces.

Block Diagram

Figure 1. DS90CF563 Figure 2. DS90CF564

DS90CF563MTD is no longer available. See Package Number DGG0048A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90CF563, DS90CF564

www.ti.com

SNLS107E –JULY 1997–REVISED APRIL 2013

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

Input Clamp Voltage I

= −18 mA −0.7 −1.5 V

Input Current V

= V

, GND, 2.5V or 0.4V ±5.1 ±10 μA

Output Short Circuit Current V

OUT

= 0V −120 mA

LVDS DRIVER DC SPECIFICATIONS

Differential Output Voltage R

= 100Ω 250 290 450 mV

ΔV

Change in V

between

35 mV

Complementary Output States

Common Mode Voltage 1.1 1.25 1.37 V

ΔV

Change in V

between

35 mV

Complementary Output States

High Level Output Voltage 1.3 1.6 V

Low Level Output Voltage 0.9 1.01 V

Output Short Circuit Current V

OUT

= 0V, R

= 100Ω −2.9 −5 mA

Output TRI-STATE Current Power Down = 0V, V

OUT

= 0V or V

±1 ±10 μA

LVDS RECEIVER DC SPECIFICATIONS

Differential Input High Threshold V

= +1.2V +100 mV

Differential Input Low Threshold −100 mV

Input Current V

= +2.4V V

= 5.5V ±10 μA

= 0V ±10 μA

TRANSMITTER SUPPLY CURRENT

CCTW

Transmitter Supply Current, R

= 100Ω, C

= 5 pF, f = 32.5 MHz 49 63 mA

Worst Case Worst Case Pattern

f = 37.5 MHz 51 64 mA

(Figure 3, Figure 5)

f = 65 MHz 70 84 mA

CCTG

Transmitter Supply Current, R

= 100Ω, C

= 5 pF, f = 32.5 MHz 40 55 mA

16 Grayscale 16 Grayscale Pattern

f = 37.5 MHz 41 55 mA

(Figure 4, Figure 5)

f = 65 MHz 55 67 mA

CCTZ

Transmitter Supply Current, Power Down = Low

1 25 μA

Power Down

RECEIVER SUPPLY CURRENT

CCRW

Receiver Supply Current, C

= 8 pF, f = 32.5 MHz 64 77 mA

Worst Case Worst Case Pattern f = 37.5 MHz 70 85 mA

(Figure 3, Figure 6) f = 65 MHz 110 140 mA

CCRG

Receiver Supply Current, C

= 8 pF, f = 32.5 MHz 35 55 mA

16 Grayscale 16 Grayscale Pattern f = 37.5 MHz 37 55 mA

(Figure 4, Figure 6) f = 65 MHz 55 67 mA

CCRZ

Receiver Supply Current, Power Down = Low 1 10 μA

Power Down

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

LLHT LVDS Low-to-High Transition Time (Figure 5) 0.75 1.5 ns

LHLT LVDS High-to-Low Transition Time (Figure 5) 0.75 1.5 ns

TCIT TxCLK IN Transition Time (Figure 7) 8 ns

TCCS TxOUT Channel-to-Channel Skew

(1)

(Figure 8) 350 ps

(1) This limit based on bench characterization.

Product Folder Links: DS90CF563 DS90CF564

DS90CF563, DS90CF564

SNLS107E –JULY 1997–REVISED APRIL 2013

www.ti.com

Transmitter Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

TCCD TxCLK IN to TxCLK OUT Delay @ 25°C, V

= 5.0V 3.5 8.5 ns

(Figure 11)

TCIP TxCLK IN Period (Figure 9) 15 T 50 ns

TCIH TxCLK IN High Time (Figure 9) 0.35T 0.5T 0.65T ns

TCIL TxCLK IN Low Time (Figure 9) 0.35T 0.5T 0.65T ns

TSTC TxIN Setup to TxCLK IN (Figure 9 ) f = 65 MHz 5 3.5 ns

THTC TxIN Hold to TxCLK IN (Figure 9) 2.5 1.5 ns

TPDD Transmitter Powerdown Delay (Figure 20) 100 ns

TPLLS Transmitter Phase Lock Loop Set (Figure 13) 10 ms

TPPos0 Transmitter Output Pulse Position 0 (Figure 15) −0.30 0 0.30 ns

TPPos1 Transmitter Output Pulse Position 1 1.70 1/7 T

clk

2.50 ns

TPPos2 Transmitter Output Pulse Position 2 3.60 2/7 T

clk

4.50 ns

TPPos3 Transmitter Output Pulse Position 3 5.90 3/7 T

clk

6.75 ns

TPPos4 Transmitter Output Pulse Position 4 8.30 4/7 T

clk

9.00 ns

TPPos5 Transmitter Output Pulse Position 5 10.40 5/7 T

clk

11.10 ns

TPPos6 Transmitter Output Pulse Position 6 12.70 6/7 T

clk

13.40 ns

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Units

CLHT CMOS/TTL Low-to-High Transition Time (Figure 6) 2.5 4.0 ns

CHLT CMOS/TTL High-to-Low Transition Time (Figure 6) 2.0 3.5 ns

RCOP RxCLK OUT Period 15 T 50 ns

RCOH RxCLK OUT High Time f = 65 MHz 7.8 9 ns

RCOL RxCLK OUT Low Time f = 65 MHz 3.8 5 ns

RSRC RxOUT Setup to RxCLK OUT f = 65 MHz 2.5 4.2 ns

RHRC RxOUT Hold to RxCLK OUT f = 65 MHz 4.0 5.2 ns

RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, V

= 5.0V 6.4 10.7 ns

(Figure 12)

RPLLS Receiver Phase Lock Loop Set (Figure 14) 10 ms

RSKM RxIN Skew Margin

(1)

(Figure 16) V

= 5V, T

=25°C 600 ps

RPDD Receiver Powerdown (Figure 19) 1 μs

(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter

output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on

type/length and source clock (TxCLK IN) jitter.

RSKM ≥ cable skew (the, length) + source clock jitter (cycle to cycle)

Product Folder Links: DS90CF563 DS90CF564

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