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DVI / HDMI

Source

text

DS16EV5110

DeS / Display

Controller

DVI / HDMI Sink

20m 28 AWG DVI / HDMI Cable

DS16EV5110

www.ti.com

SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

DS16EV5110 Video Equalizer (3D+C) for DVI, HDMI Sink-Side Applications

Check for Samples: DS16EV5110

FEATURES

APPLICATIONS

• 8 Levels of Equalization Settable by 3 Pins or

• Sink-Side Video Applications

Through the SMBus Interface

• Projectors

• DC-Coupled Inputs and Outputs

• High Definition Displays

• Optimized for Operation From 250 Mbps to

2.25 Gbps in Support of UXGA, 480 I/P, 720 I/P, DESCRIPTION

1080 I, and 1080 P With 8, 10, and 12-Bit Color

The DS16EV5110 is a multi-channel equalizer

Depth Resolutions

optimized for video cable extension sink-side

applications. It operates between 250Mbps and

• Two DS16EV5110 Devices Support DVI/HDMI

2.25Gbps with common applications at 1.65Gbps and

Dual Link

2.25Gbps (per data channel). It contains three

• DVI 1.0, and HDMI 1.3a Compatible TMDS

Transition-Minimized Differential Signaling (TMDS)

Interface

data channels and one clock channel as commonly

found in DVI and HDMI cables. It provides

• Clock Channel Signal Detect (LOS)

compensation for skin-effect and dielectric losses, a

• Enable for Power Savings Standby Mode

common phenomenon when transmitting video on

• System Management Bus (SMBus) Provides

commercially available high definition video cables.

Control of Boost, Output Amplitude, Enable,

The inputs conform to DVI and HDMI requirements

and Clock Channel Signal Detect Threshold

and features programmable levels of input

• Low Power Consumption: 475mW (Typical)

equalization. The programmable levels of

• 0.13 UI Total Jitter at 1.65 Gbps Including

equalization provide optimal signal boost and reduces

inter-symbol interference. Eight levels of boost are

Cable

selectable via a pin interface or by the optional

• Single 3.3V Power Supply

System Management Bus.

• Small 7mm x 7mm, 48-Pin Leadless WQFN

The clock channel is optimized for clock rates of up to

Package

225 MHz and features a signal detect circuit. To

• -40°C to +85°C Operating Temperature Range

maximize noise immunity, the DS16EV5110 features

• Extends TMDS Cable Reach Over:

a signal detector with programmable thresholds. The

threshold is adjustable through a System

1. > 40 Meters 24 AWG DVI Cable (1.65Gbps)

Management Bus (SMBus) interface.

2. > 20 Meters 28 AWG DVI Cable (1.65Gbps)

The DS16EV5110 also provides support for system

3. > 20 Meters Cat5/Cat5e/Cat6 Cables

power management via output enable controls.

(1.65Gbps)

Additional controls are provided via the SMBus

4. > 20 Meters 28 AWG HDMI Cables

enabling customization and optimization for specific

(2.25Gbps)

applications requirements. These controls include

programmable features such as output amplitude and

boost controls as well as system level diagnostics.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS16EV5110

SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

www.ti.com

PIN DESCRIPTIONS

Pin Name Pin Number I/O

(1)

, Type Description

HIGH SPEED DIFFERENTIAL I/O

C_IN− 1 I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50Ω terminating

C_IN+ 2 resistor connects C_IN+ to VDD and C_IN- to VDD.

D_IN0− 4 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating

D_IN0+ 5 resistor connects D_IN0+ to VDD and D_IN0- to VDD.

D_IN1− 8 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating

D_IN1+ 9 resistor connects D_IN1+ to VDD and D_IN1- to VDD.

D_IN2− 11 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating

D_IN2+ 12 resistor connects D_IN2+ to VDD and D_IN2- to VDD.

C_OUT- 36 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.

C_OUT+ 35

D_OUT0− 33 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.

D_OUT0+ 32

D_OUT1– 29 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.

D_OUT1+ 28

D_OUT2− 26 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.

D_OUT2+ 25

Equalization Control

BST_0 23 I, LVCMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0, BST_1,

BST_1 14 and BST_2 are internally pulled Low. See Table 2.

BST_2 37

Device Control

EN 44 I, LVCMOS Enable Equalizer input. When held High, normal operation is selected. When held Low,

standby mode is selected. EN is internally pulled High. Signal is global to all Data and Clock

channels.

FEB 21 I, LVCMOS Force External Boost. When held High, the equalizer boost setting is controlled by the

BST_[0:2] pins. When held Low, the equalizer boost level is controlled through the SMBus

(see Table 1) control pins. FEB is internally pulled High.

SD 45 O, LVCMOS Equalizer Clock Channel Signal Detect Output. Produces a High when signal is detected.

POWER

3, 6, 7, Power V

pins should be tied to the V

plane through a low inductance path. A 0.1µF bypass

10, 13, capacitor should be connected between each V

pin to the GND planes.

15, 46

GND 22, 24, GND Ground reference. GND should be tied to a solid ground plane through a low impedance

27, 30, path.

31, 34

Exposed Pad DAP GND The exposed pad at the center of the package must be connected to the ground plane.

System Management Bus (SMBus) Interface Control Pins

SDA 18 IO, LVCMOS SMBus Data Input / Output. Internally pulled High to 3.3V with High-Z pull up.

SDC 17 I, LVCMOS SMBus Clock Input. Internally pulled High to 3.3V with High-Z pull up.

CS 16 I, LVCMOS SMBus Chip select. When held High, the equalizer SMBus register is enabled. When held

Low, the equalizer SMBus register is disabled. CS is internally pulled Low. CS is internally

gated with SDC.

Other

Reserv 19, 20, 38, Reserved. Do not connect.

39, 40,41,

42, 43, 47,

(1) Note: I = Input,O = Output, IO =Input/Output,

Product Folder Links: DS16EV5110

DS16EV5110

SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)(2)

Supply Voltage (V

) -0.5V to +4.0V

LVCMOS Input Voltage -0.5V + 4.0V

LVCMOS Output Voltage -0.5V to 4.0V

CML Input/Output Voltage -0.5V to 4.0V

Junction Temperature +150°C

Storage Temperature -65°C to +150°C

Lead Temperature (Soldering, 5 sec.) +260°C

HBM, 1.5 kΩ, 100 pF >8 kV

ESD Rating

CML Inputs >10 kV

Thermal Resistance θ

, No Airflow 30°C/W

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute

Maximum Numbers are ensured for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating

Voltages only.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

Recommended Operating Conditions

(1)(2)

Min Typ Max Units

Supply Voltage (V

to GND) 3.0 3.3 3.6 V

Ambient Temperature -40 25 +85 °C

(1) Typical values represent most likely parametric norms at V

= 3.3V, T

= 25°C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured.

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified.

(1)(2)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS DC SPECIFICATIONS

IH-PU

High Level Input Leakage Current LVCMOS pins with internal pull-up

-10 +10 μA

resistors

IH-PD

High Level Input Leakage Current LVCMOS pins with internal pull-

80 105 μA

down resistors

IL-PU

Low Level Input Leakage Current LVCMOS pins with internal pull-up

-20 -10 μA

resistors

IL-PD

Low Level Input Leakage Current LVCMOS pins with internal pull-

-10 +10 μA

down resistors

High Level Input Voltage 2.0 VDD V

Low Level Input Voltage 0 0.8 V

High Level Output Voltage SD Pin, I

= -3mA 2.4 V

Low Level Output Voltage SD Pin, I

= 3mA 0.4 V

POWER

PD Power Dissipation EN = High, Device Enabled 475 700 mW

EN = Low, Power Down Mode 70 mW

(1) Typical values represent most likely parametric norms at V

= 3.3V, T

= 25°C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured.

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.

Product Folder Links: DS16EV5110

DS16EV5110

www.ti.com

SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless other specified.

(1)(2)

Symbol Parameter Conditions Min Typ Max Units

N Supply Noise Tolerance

(3)

DC to 50MHz 100 mV

P-P

CML INPUTS

Input Voltage Swing (Launch Measured differentially at TPA

800 1200 mV

P-P

Amplitude) (Figure 2)

ICMDC

Input Common-Mode Voltage DC-Coupled Requirement

-0.3 V

-0.2 V

Measured at TPA (Figure 2)

Input Voltage Swing Measured differentially at TPB

120 mV

P-P

(Figure 2)

Differential Input Return Loss 100 MHz– 825 MHz, with fixture's

10 dB

effect de-embedded

Input Resistance IN+ to VDD and IN− to VDD 45 50 55 Ω

CML OUTPUTS

Output Voltage Swing Measured differentially with OUT+

and OUT− terminated by 50Ω to 800 1200 mV

P-P

VDD

OCM

Output common-mode Voltage Measured Single-ended V

-0.3 V

-0.2 V

, t

Transition Time 20% to 80% of differential output

voltage, measured within 1" from 75 240 ps

output pins.

CCSK

Inter Pair Channel-to-Channel Difference in 50% crossing

Skew (all 4 Channels) between shortest and longest 25 ps

channels

Latency 350 ps

OUTPUT JITTER

TJ1 Total Jitter at 1.65 Gbps 20m 28 AWG STP DVI Cable

Data Paths 0.13 0.17 UI

P-P

EQ Setting 0x04 PRBS7

(4) (5) (6)

TJ2 Total Jitter at 2.25 Gbps 20m 28 AWG STP DVI Cable

Data Paths 0.2 UI

P-P

EQ Setting 0x04 PRBS7

(4) (5) (6)

TJ3 Total Jitter at 165 MHz Clock Paths

0.165 UI

P-P

Clock Pattern

(4) (5) (6)

TJ4 Total Jitter at 225 MHz Clock Paths

0.165 UI

P-P

Clock Pattern

(4) (5) (6)

RJ Random Jitter See

(6) (7)

3 ps

rms

BIT RATE

CLK

Clock Frequency Clock Path

(4)

25 225 MHz

BR Bit Rate Data Path

(4)

0.25 2.25 Gbps

(3) Allowed supply noise (mV

P-P

sine wave) under typical conditions.

(4) Specification is ensured by characterization and is not tested in production.

(5) Deterministic jitter is measured at the differential outputs (TPC of Figure 2), minus the deterministic jitter before the test channel (TPA of

Figure 2). Random jitter is removed through the use of averaging or similar means.

(6) Total Jitter is defined as peak-to-peak deterministic jitter from

()

+ 14.2 times random jitter in ps

rms

(7) Random jitter contributed by the equalizer is defined as sq rt (J

OUT

− J

). J

OUT

is the random jitter at equalizer outputs in ps

rms

, see

TPC of Figure 2; J

is the random jitter at the input of the equalizer in ps

rms

, see TPA of Figure 2.

Product Folder Links: DS16EV5110

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