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TI-TS3DS26227.pdf
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TI-TS3DS26227.pdf
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3DS26227
SCDS224B –JUNE 2008–REVISED OCTOBER 2010
HIGH-BANDWIDTH DUAL SPDT DIFFERENTIAL SIGNAL SWITCH
WITH INPUT LOGIC TRANSLATION
1
1 FEATURES
1
• High-Bandwidth Data Paths – Up to 800 MHz
• Specified Break-Before-Make Switching
• Control Inputs Reference to V
IO
• Low Charge Injection
• Excellent ON-State Resistance Matching
• Low Total Harmonic Distortion (THD)
• 2.3-V to 3.6-V Power Supply (V
+
)
• 1.65-V to 1.95-V Logic Supply (V
IO
)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 4000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
– 200-V Machine Model (A115-A)
2 APPLICATIONS
• Cell Phones
• PDAs
• Portable Instrumentation
• Low-Voltage Differential Signal Routing
• Mobile Industry Processor Interface (MIPI) Signal
Routing
![](https://csdnimg.cn/release/download_crawler_static/87230214/bg2.jpg)
8
1
2
3
4 9
6
5
7
11
10
12
1
2
3
A B
C
D
2
TS3DS26227
SCDS224B –JUNE 2008–REVISED OCTOBER 2010
www.ti.com
Product Folder Links: TS3DS26227
Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
YZT PACKAGE
(BOTTOM VIEW)
Table 1. TERMINAL ASSIGNMENTS
A B C D
1 IN1 NO1 COM1 NC1
2 V
IO
GND GND V
+
3 IN2 NO2 COM2 NC2
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
3 DESCRIPTION/ORDERING INFORMATION
The TS3DS26227 is a dual single-pole double-throw (SPDT) analog switch that is designed to operate from
2.3 V to 3.6 V. The device offers high-bandwidth data paths, and a break-before-make feature to prevent signal
distortion during the transferring of a signal from one path to another. The device has excellent total harmonic
distortion (THD) performance and consumes very low power. These features make this device suitable for
portable applications.
The TS3DS26227 has a separate logic supply pin (V
IO
) that operates from 1.65 V to 1.95 V. V
IO
powers the
control circuitry, which allows the TS3DS26227 to be controlled by 1.8-V signals.
Table 2. ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZT (Pb-free)
Tape and reel TS3DS26227YZTR
![](https://csdnimg.cn/release/download_crawler_static/87230214/bg3.jpg)
COM1
IN1
(S )ee Note A
NC1
NO1
COM2
IN2
(S )ee Note A
NO2
NC2
3
TS3DS26227
www.ti.com
SCDS224B –JUNE 2008–REVISED OCTOBER 2010
Product Folder Links: TS3DS26227
Submit Documentation FeedbackCopyright © 2008–2010, Texas Instruments Incorporated
(1) V
+
= 2.7 V, T
A
= 25°C
Table 3. SUMMARY OF CHARACTERISTICS
(1)
Configuration
Dual 2:1
Multiplexer/Demultiplexer
(2 × SPDT)
Number of channels 2
ON-state resistance (r
on
) 5 Ω max
ON-state resistance match (Δr
on
) 0.1 Ω max
ON-state resistance flatness [r
on(flat)
] 3 Ω max
Turn-on/turn-off time (t
ON
/t
OFF
) 9 ns/4 ns
Break-before-make time (t
BBM
) 8 ns
Charge injection (Q
C
) 5.5 pC
Bandwidth (BW) 800 MHz
OFF isolation (O
ISO
) –40 dB
Crosstalk (X
TALK
) –39 dB
Leakage current [I
NO(OFF)
/I
NC(OFF)
] ±5 nA
Power-supply current (I
+
) ±20 nA
Package options 12-bump WCSP
Table 4. FUNCTION TABLE
IN
NC TO COM,
COM TO NC
NO TO COM,
COM TO NO
L ON OFF
H OFF ON
LOGIC DIAGRAM
A. IN1 and IN2 are control inputs referenced to V
IO
.
![](https://csdnimg.cn/release/download_crawler_static/87230214/bg4.jpg)
4
TS3DS26227
SCDS224B –JUNE 2008–REVISED OCTOBER 2010
www.ti.com
Product Folder Links: TS3DS26227
Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
(4) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(5) This value is limited to 5.5 V maximum.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
3.1 ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
+
V
IO
Supply voltage range
(3)
–0.5 4.6 V
V
NC
V
NO
V
COM
Analog voltage range
(3) (4) (5)
–0.5 V
+
+ 0.5 V
I
K
Analog port diode current
V
NC
, V
NO
, V
COM
< 0, or V
NC
,
V
NO
, V
COM
> V
+
+ 0.5
–50 50 mA
I
NC
I
NO
I
COM
On-state switch current V
NC
, V
NO
, V
COM
= 0 to V
+
–64 64
mA
On-state peak switch current –100 100
V
I
Digital input voltage range –0.5 V
IO
+ 0.5 V
I
IK
Digital input clamp current
(3) (4)
V
I
< 0, or V
I
> V
IO
+ 0.5 –50 50 mA
I
+
Continuous current through V
+
–100 100 mA
I
GND
Continuous current through GND –100 100 mA
θ
JA
Package thermal impedance
(6)
YZT package TBD °C/W
T
stg
Storage temperature range –65 150 °C
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