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Serial Audio

Receiver

2x Stereo

Serial Audio

Receiver

2x Stereo

Serial Audio

Transciever

Stereo

4ch ASRC

Fixed Flow

Digital Audio

Processor

(DAP)

10ch input

8ch Processor

8ch Output Mixer

Clocks

(Osc, PLL

etc)

12.288

8ch PWM

Generator

+ Headphone

(PWM)

Bypass

MCU

I2C

Control

Power

Supply

Volume

Control

(PSVC)

Energy

Manager

(EMO)

Power

SDA

SCL

SDOUT/SDIN5

SDIN1

SDIN2

SCLK

LRCLK

SDIN2-1

SDIN2-2

SCLKO /SCLKIN_2

LRCLKO / LRCKIN_2

OSCRES

PLL_FLTM

PLL_FLTP

MCLK

EMO1

ASEL_EMO2

PSVC/MCLKO

VR_DIG

VR_PWM

VR_ANA

AVDD

AVDD_PWM

AVSS

AVSS_PWM

DVDD1

DVDD2

DVSS1

DVSS2

/PDN

PWM_HPM_L&R

PWM_HPP_L&R

/BKND_ERR

PWM_x_1

through 8

ASEL_EMO2

VALID

/MUTE

TEST

RESET

/HP_SEL

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

TAS5548

ZHCSAJ3A –NOVEMBER 2012–REVISED APRIL 2015

TAS5548 具具有有异异步步 ASRC 和和 PWM 输输出出的的 8 通通道道 HD 可可兼兼容容音音频频处处理理器器

1 特特性性 – 可调调制限制

• 一般特性

2 应应用用

– 8 通道异步采样率转换器

与大多数数字音频解码器的无缝对接

– 针对 32-192kHz（ARSC 至 96kHz）的 8 通道

音频处理

3 说说明明

– 频率为 192kHZ 的 4 通道本地音频处理

TAS5548 是一款具有数字音频处理功能和采样率转换

– 用于实现 DTS-HD 兼容性的 30kHz 音频带宽

器的 8 通道数字脉宽调制器 (PWM)，具备先进的性能

– 用于总体系统功率控制的能量管理器

和较高的系统集成度。 TAS5548被设计用于支持

– 电源音量控制

DTS-HD 规格蓝光 HTiB 应用。 ASRC 包含两个独立

• 音频输入或输出

的模块，每个模块可处理 4 个通道。因此，它能够支

– 多达 5 个同步串行音频输入（10 个通道）

持多达两个不同的输入采样率。

– 多达 1 个同步串行音频输出（2 个通道）

德州仪器 (TI) 功率级设计用于与 TAS5548 无缝配合工

– 当与外部晶振一起使用时的 I2S 主控模式

作。 TAS5548还提供一个高性能、差分输出以驱动一

– 具有自动/手工采样速率检测的受控模式 32-

个外部、差分输入、模拟头戴式耳机放大器。

192kHz

– 8 个可支持 AD 或 BD 调制的差分 PWM 输出

针对 48，96 和 192kHz 数据，TAS5548支持开关速率

– 两个差分 PWM 头戴式耳机输出

为 384kHz 的 AD，BD 和三重调制。必须采用频率为

– 针对外部无线子

12.288MHz 的外部晶振。 TAS5548 还具备电源容量

– PWM 输出的 I2S 支持单端 (S.E.) 或桥接负载

控制 (PSVC) 功能，可增大低功率级的动态范围，并且

(BTL)

在与闭环 PWM 输入功率级一起使用时，可作为 G 类

• 音频处理

电源的一部分。

– 音量控制范围为 18dB 至 -127dB（主控和八通

器器件件信信息息

(1)

道音量）

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

– 具有 ±18dB 范围、可选角频率的低音和高音音

TAS5548 HTSSOP (56) 14.00mm x 6.10mm

质控制

– 可配置响度补偿

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

– 两个具有两个阈值、两个偏移和三个斜坡的动态

方方框框图图

范围压缩器

– 每个通道七个二阶无限脉冲响应滤波器

(Biquad)

• PWM 处理

– >105dB 的动态范围

– 总谐波失真 (THD)+N<0.1% (0-40kHz)

– 20Hz - 40kHz，针对 32KHz - 192KHz 的白噪

声基准

– 具有可编程阈值和针对无噪声运行持续时间的灵

活自动逻辑

– 高性能应用中的电源音量控制 (PSVC)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLES270

TAS5548

ZHCSAJ3A –NOVEMBER 2012–REVISED APRIL 2015

www.ti.com.cn

目目录录

7.1 Overview ................................................................. 14

1 特特性性.......................................................................... 1

7.2 Functional Block Diagram ....................................... 14

2 应应用用.......................................................................... 1

7.3 Feature Description................................................. 16

3 说说明明.......................................................................... 1

7.4 Device Functional Modes........................................ 25

4 修修订订历历史史记记录录 ........................................................... 2

7.5 Programming........................................................... 48

5 Pin Configuration and Functions......................... 3

7.6 Register Maps......................................................... 53

6 Specifications......................................................... 6

8 Application and Implementation ........................ 95

6.1 Absolute Maximum Ratings ..................................... 6

8.1 Application Information............................................ 95

6.2 ESD Ratings.............................................................. 6

8.2 Typical Applications ................................................ 95

6.3 Recommended Operating Conditions....................... 6

8.3 Do’s and Don’ts..................................................... 102

6.4 Thermal Information.................................................. 6

8.4 Initialization Set Up ............................................... 102

6.5 Electrical Characteristics........................................... 7

9 Power Supply Recommendations.................... 103

6.6 Dynamic Performance ............................................. 7

9.1 Power Supply........................................................ 103

6.7 SRC Performance..................................................... 7

9.2 Energy Manager.................................................... 103

6.8 Timing I

C Serial Control Port Operation.................. 8

9.3 Programming Energy Manager............................. 104

6.9 Reset Timing (RESET) ............................................. 8

10 Layout................................................................. 105

6.10 Power-Down (PDN) Timing..................................... 8

10.1 Layout Guidelines ............................................... 105

6.11 Back-End Error (BKND_ERR) ............................... 8

10.2 Layout Example .................................................. 106

6.12 Mute Timing (MUTE).............................................. 9

11 器器件件和和文文档档支支持持 ................................................... 108

6.13 Headphone Select (HP_SEL) ................................ 9

11.1 文档支持.............................................................. 108

6.14 Switching Characteristics - Clock Signals............... 9

11.2 商标 ..................................................................... 108

6.15 Switching Characteristics - Serial Audio Port ....... 9

11.3 静电放电警告....................................................... 108

6.16 Volume Control .................................................... 10

11.4 术语表 ................................................................. 108

6.17 Typical Characteristics.......................................... 13

12 机机械械封封装装和和可可订订购购信信息息 ........................................ 108

7 Detailed Description............................................ 14

4 修修订订历历史史记记录录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (November 2012) to Revision A Page

• 已添加 ESD

额定值

表，

特性描述

部分，

器件功能模式

，

应用和实施

部分，

电源相关建议

部分，

布局

部分，

器件和文档

支持

部分以及

机械、封装和可订购信息

部分。........................................................................................................................ 1

• Added the Thermal Information table ..................................................................................................................................... 6

• Updated Figure 23 ............................................................................................................................................................... 29

• Updated Figure 24................................................................................................................................................................ 30

• Updated Table 12 ................................................................................................................................................................. 46

PWM_HPM_L

PWM_HPP_R

AVSS

PLL_FLTM

PLL_FLTP

SDIN1

VR_ANA

SDIN2

AVDD

ASEL_EMO2

SCLK

SDIN2_1 (SDIN3)

XTALI

XTALO

DVSS2

DVDD2

EMO1

RESET

HP_SEL

PDN

MUTE

VR_DIG

LRCLK

SDA

SCL

PWM_HPP_L

PWM_HPM_R

28 29

PWM_P_6

PWM_M_6

PWM_P_5

PWM_M_5

VR_PWM

AVSS_PWM

AVDD_PWM

PWM_P_8

PWM_M_8

PWM_P_7

PWM_M_7

PWM_P_4

PWM_M_4

PWM_P_3

PWM_M_3

PWM_P_2

PWM_M_2

PWM_P_1

VALID

DVDD1

PWM_M_1

DVSS1

BKND_ERR

PSVC/MLCK

TEST

LRCLKO (LRCK#2)

SCLKO (SCLK#2)

SDOUT (SDIN5)

SDIN2_2 (SDIN4)

TAS5548

www.ti.com.cn

ZHCSAJ3A –NOVEMBER 2012–REVISED APRIL 2015

5 Pin Configuration and Functions

TAS5548 DCA Package

56-Pin HTSSOP

Top View

Pin Functions

5-V

TYPE TERMINATION DESCRIPTION

TOLERANT

NAME NO.

ASEL_EMO2 10 DIO Pullup I2C Address Select. Address will 0X34/0X36 with the value of pin being "0' or

"1" during de-assertion of reset. Can be programmed to be an output (as energy

manager output for subwoofer)

AVDD 9 P Analog supply (3.3 V) for PLL.

AVDD_PWM 50 P 3.3-V analog power supply for PWM. This terminal can be connected to the

same power source used to drive power terminal DVDD; but to achieve low PLL

jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-μF low-ESR

capacitor.

AVSS 5 P Analog ground

AVSS_PWM 51 P Analog ground for PWM. Must have direct return Cu path to analog 3.3V supply

for optimized performance.

BKND_ERR 34 DI Pullup Active-low. A back-end error sequence is generated by applying logic low to this

terminal. The BKND_ERR results in no change to I2C parameters, with all H-

bridge drive signals going to a hard-mute state (Non PWM Switching).

DVDD1 35 P 3.3-V digital power supply. (It is recommended that decoupling capacitors of

0.1 μF and 10 μF be mounted close to this pin).

DVDD2 14 P 3.3-V digital power supply for PWM. (It is recommended that decoupling

capacitors of 0.1 μF and 10 μF be mounted close to this pin).

DVSS1 36 P Digital ground 1

DVSS2 13 P Digital ground 2

EMO1 15 DO Energy Manger Output interrupt - Asserted high when threshold is exceeded.

TAS5548

ZHCSAJ3A –NOVEMBER 2012–REVISED APRIL 2015

www.ti.com.cn

Pin Functions (continued)

5-V

TYPE TERMINATION DESCRIPTION

TOLERANT

NAME NO.

HP_SEL 17 DI 5 V Pullup Headphone/speaker selector. When a logic low is applied, the headphone is

selected (speakers are off). When a logic high is applied, speakers are selected

(headphone is off).

LRCLK 22 DI 5 V Pulldown Serial-audio data left/right clock (sampling-rate clock)

LRCLKO / 31 DIO 5V Pulldown LRCLK for I2S OUT. Can also be used as LRCKIN_2 (I2S Input for SDIN2_x

LRCKIN_2 and SRC Bank 2)

XTALI 11 DI 1.8 V XTAL input. Connect to external 12.288 MHz XTAL

MUTE 19 DI 5 V Pullup Soft mute of outputs, active-low (muted signal = a logic low, normal operation =

a logic high). The mute control provides a noiseless volume ramp to silence.

Releasing mute provides a noiseless ramp to previous volume.

XTALO 12 DO XTAL input. Connect to external 12.288 MHz XTAL

PDN 18 DI 5 V Pullup Power down, active-low. PDN powers down all logic and stops all clocks

whenever a logic low is applied. The I2C parameters are preserved through a

power-down cycle, as long as RESET is not active.

PLL_FLTM 6 AIO PLL negative filter.

PLL_FLTP 7 AIO PLL positive filter.

PSVC/MCLKO 33 DO Power-supply volume control PWM output or MCKO for external ADC (SDIN5

Source)

PWM_HPM_L 1 DO PWM left-channel headphone (differential –)

PWM_HPM_R 3 DO PWM right-channel headphone (differential –)

PWM_HPP_L 2 DO PWM left-channel headphone (differential +)

PWM_HPP_R 4 DO PWM right-channel headphone (differential +)

PWM_M_1 38 DO PWM 1 output (differential –)

PWM_M_2 40 DO PWM 2 output (differential –)

PWM_M_3 42 DO PWM 3 output (differential –)

PWM_M_4 44 DO PWM 4 output (differential –)

PWM_M_5 53 DO PWM 5 output (lineout L) (differential –)

PWM_M_6 55 DO PWM 6 output (lineout R) (differential –)

PWM_M_7 46 DO PWM 7 output (differential –)

PWM_M_8 48 DO PWM 8 output (differential –)

PWM_P_1 39 DO PWM 1 output (differential +)

PWM_P_2 41 DO PWM 2 output (differential +)

PWM_P_3 43 DO PWM 3 output (differential +)

PWM_P_4 45 DO PWM 4 output (differential +)

PWM_P_5 54 DO PWM 5 output (lineout L) (differential +)

PWM_P_6 56 DO PWM 6 output (lineout R) (differential +)

PWM_P_7 47 DO PWM 7 output (differential +)

PWM_P_8 49 DO PWM 8 output (differential +)

RESET 16 DI 5 V Pullup System reset input, active-low. A system reset is generated by applying a logic

low to this terminal. RESET is an asynchronous control signal that restores the

TAS5548 to its default conditions, sets the valid output low, and places the

PWM in the hard-mute state (Non PWM Switching). Master volume is

immediately set to full attenuation. On the release of RESET, if PDN is high, the

system performs a 4- to 5-ms device initialization and sets the volume at mute.

SCL 21 DI 5 V

C serial-control clock input/output

SCLK 23 DI 5 V Pulldown Serial-audio data clock (shift clock) input

SCLKO / 30 DIO 5V Pulldown Serial data clock out. I2S bit clock out. Can also be used as SCLKIN_2 (I2S

SCLKIN_2 Input for SDIN2_x and SRC Bank 2)

SDA 20 DIO 5 V

C serial-control data-interface input/output

SDIN1 24 DI 5 V Pulldown Serial-audio data bank 1 input 1 is one of the serial-data input ports and goes

into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of

inputting data at 64 f

SDIN2 25 DI 5 V Pulldown Serial-audio data bank 1 input 2 is one of the serial-data input ports and goes

into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of

inputting data at 64 f

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