DS90C031B
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SNLS051B –MARCH 1999–REVISED MARCH 2013
DS90C031B LVDS Quad CMOS Differential Line Driver
Check for Samples: DS90C031B
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FEATURES
DESCRIPTION
The DS90C031B is a quad CMOS differential line
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• >155.5 Mbps (77.7 MHz) switching rates
driver designed for applications requiring ultra low
• High impedance LVDS outputs with power-off
power dissipation and high data rates. The device
• ±350 mV differential signaling
supports data rates in excess of 155.5 Mbps (77.7
MHz) and uses Low Voltage Differential Signaling
• Ultra low power dissipation
(LVDS) technology.
• 400 ps maximum differential skew (5V, 25°C)
The DS90C031B accepts TTL/CMOS input levels and
• 3.5 ns maximum propagation delay
translates them to low voltage (350 mV) differential
• Industrial operating temperature range
output signals. In addition the driver supports a TRI-
• Pin compatible with DS26C31, MB571 (PECL)
STATE function that may be used to disable the
and 41LG (PECL)
output stage, disabling the load current, and thus
dropping the device to an ultra low idle power state of
• Conforms to ANSI/TIA/EIA-644 LVDS standard
11 mW typical.
• Offered in narrow body SOIC package
In addition, the DS90C031B provides power-off high
• Fail-safe logic for floating inputs
impedance LVDS outputs. This feature assures
minimal loading effect on the LVDS bus lines when
V
CC
is not present.
The DS90C031B and companion line receiver
(DS90C032B) provide a new alternative to high
power pseudo-ECL devices for high speed point-to-
point interface applications.
Connection Diagram
Functional Diagram
Figure 1. Dual-In-Line
See Package Number D (R-PDSO-G16)
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PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.