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TI-DS90C031B.pdf
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LVDS驱动器
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DS90C031B
www.ti.com
SNLS051B –MARCH 1999–REVISED MARCH 2013
DS90C031B LVDS Quad CMOS Differential Line Driver
Check for Samples: DS90C031B
1
FEATURES
DESCRIPTION
The DS90C031B is a quad CMOS differential line
2
• >155.5 Mbps (77.7 MHz) switching rates
driver designed for applications requiring ultra low
• High impedance LVDS outputs with power-off
power dissipation and high data rates. The device
• ±350 mV differential signaling
supports data rates in excess of 155.5 Mbps (77.7
MHz) and uses Low Voltage Differential Signaling
• Ultra low power dissipation
(LVDS) technology.
• 400 ps maximum differential skew (5V, 25°C)
The DS90C031B accepts TTL/CMOS input levels and
• 3.5 ns maximum propagation delay
translates them to low voltage (350 mV) differential
• Industrial operating temperature range
output signals. In addition the driver supports a TRI-
• Pin compatible with DS26C31, MB571 (PECL)
STATE function that may be used to disable the
and 41LG (PECL)
output stage, disabling the load current, and thus
dropping the device to an ultra low idle power state of
• Conforms to ANSI/TIA/EIA-644 LVDS standard
11 mW typical.
• Offered in narrow body SOIC package
In addition, the DS90C031B provides power-off high
• Fail-safe logic for floating inputs
impedance LVDS outputs. This feature assures
minimal loading effect on the LVDS bus lines when
V
CC
is not present.
The DS90C031B and companion line receiver
(DS90C032B) provide a new alternative to high
power pseudo-ECL devices for high speed point-to-
point interface applications.
Connection Diagram
Functional Diagram
Figure 1. Dual-In-Line
See Package Number D (R-PDSO-G16)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
![](https://csdnimg.cn/release/download_crawler_static/87429681/bg2.jpg)
DS90C031B
SNLS051B –MARCH 1999–REVISED MARCH 2013
www.ti.com
Driver Truth Table
Enables Input Outputs
EN EN* D
IN
D
OUT+
D
OUT−
L H X Z Z
L L H
All other combinations of ENABLE
inputs
H H L
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) −0.3V to +6V
Input Voltage (D
IN
) −0.3V to (V
CC
+ 0.3V)
Enable Input Voltage (EN, EN*) −0.3V to (V
CC
+ 0.3V)
Output Voltage (D
OUT+
, D
OUT−
) −0.3V to +5.8V
Short Circuit Duration (D
OUT+
, D
OUT−
) Continuous
Maximum Package Power Dissipation at +25°C 1068 mW
Derate Power Dissipation 8.5 mW/°C above +25°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range, Soldering (4 seconds) +260°C
Maximum Junction Temperature +150°C
ESD Rating
HBM, 1.5 kΩ, 100 pF ≥ 2kV
EIAJ, 0 Ω, 200 pF ≥ 250V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device
operation.
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (V
CC
) +4.5 +5.0 +5.5 V
Operating Free Air Temperature (T
A
) −40 +25 +85 °C
2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90C031B
![](https://csdnimg.cn/release/download_crawler_static/87429681/bg3.jpg)
DS90C031B
www.ti.com
SNLS051B –MARCH 1999–REVISED MARCH 2013
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
(1) (2)
Symbol Parameter Test Conditions Pin Min Typ Max Units
V
OD1
Differential Output Voltage R
L
= 100Ω (Figure 2) D
OUT−
, 250 345 450 mV
D
OUT+
ΔV
OD1
Change in Magnitude of V
OD1
for 4 35 |mV|
Complementary Output States
V
OS
Offset Voltage 1.10 1.25 1.35 V
ΔV
OS
Change in Magnitude of V
OS
for 5 25 |mV|
Complementary Output States
V
OH
Output Voltage High R
L
= 100Ω 1.41 1.60 V
V
OL
Output Voltage Low 0.90 1.07 V
V
IH
Input Voltage High D
IN
, 2.0 V
CC
V
EN,
V
IL
Input Voltage Low GND 0.8 V
EN*
I
I
Input Current V
IN
= V
CC
, GND, 2.5V or 0.4V −10 ±1 +10 μA
V
CL
Input Clamp Voltage I
CL
= −18 mA −1.5 −0.8 V
I
OS
Output Short Circuit Current V
OUT
= 0V
(3)
D
OUT−
, −3.5 −5.0 mA
D
OUT+
I
OZ
Output TRI-STATE Current EN = 0.8V and EN* = 2.0V, −10 ±1 +10 μA
V
OUT
= 0V or V
CC
I
OFF
Power - Off Leakage V
O
= 0V or 2.4V, V
CC
= 0V or Open −10 ±1 +10 μA
I
CC
No Load Supply Current Drivers D
IN
= V
CC
or GND V
CC
1.7 3.0 mA
Enabled
D
IN
= 2.5V or 0.4V 4.0 6.5 mA
I
CCL
Loaded Supply Current Drivers R
L
= 100Ω (all channels), 15.4 21.0 mA
Enabled V
IN
= V
CC
or GND (all inputs)
I
CCZ
No Load Supply Current Drivers D
IN
= V
CC
or GND, 2.2 4.0 mA
Disabled EN = GND, EN* = V
CC
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: V
OD1
and ΔV
OD1
.
(2) All typicals are given for: V
CC
= +5.0V, T
A
= +25°C.
(3) Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS90C031B
![](https://csdnimg.cn/release/download_crawler_static/87429681/bg4.jpg)
DS90C031B
SNLS051B –MARCH 1999–REVISED MARCH 2013
www.ti.com
Switching Characteristics
V
CC
= +5.0V, T
A
= +25°C
(1) (2) (3)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low R
L
= 100Ω, C
L
= 5 pF 1.0 2.0 3.0 ns
(Figure 3 and Figure 4)
t
PLHD
Differential Propagation Delay Low to High 1.0 2.1 3.0 ns
t
SKD
Differential Skew |t
PHLD
– t
PLHD
| 0 80 400 ps
t
SK1
Channel-to-Channel Skew
(4)
0 300 600 ps
t
TLH
Rise Time 0.35 1.5 ns
t
THL
Fall Time 0.35 1.5 ns
t
PHZ
Disable Time High to Z R
L
= 100Ω, C
L
= 5 pF 2.5 10 ns
(Figure 5 and Figure 6)
t
PLZ
Disable Time Low to Z 2.5 10 ns
t
PZH
Enable Time Z to High 2.5 10 ns
t
PZL
Enable Time Z to Low 2.5 10 ns
(1) All typicals are given for: V
CC
= +5.0V, T
A
= +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω, t
r
≤ 6 ns, and t
f
≤ 6 ns.
(3) C
L
includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
Switching Characteristics
V
CC
= +5.0V ± 10%, T
A
= −40°C to +85°C
(1) (2) (3)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low R
L
= 100Ω, C
L
= 5 pF 0.5 2.0 3.5 ns
(Figure 3 and Figure 4)
t
PLHD
Differential Propagation Delay Low to High 0.5 2.1 3.5 ns
t
SKD
Differential Skew |t
PHLD
– t
PLHD
| 0 80 900 ps
t
SK1
Channel-to-Channel Skew
(4)
0 0.3 1.0 ns
t
SK2
Chip to Chip Skew
(5)
3.0 ns
t
TLH
Rise Time 0.35 2.0 ns
t
THL
Fall Time 0.35 2.0 ns
t
PHZ
Disable Time High to Z R
L
= 100Ω, C
L
= 5 pF 2.5 15 ns
(Figure 5 and Figure 6)
t
PLZ
Disable Time Low to Z 2.5 15 ns
t
PZH
Enable Time Z to High 2.5 15 ns
t
PZL
Enable Time Z to Low 2.5 15 ns
(1) All typicals are given for: V
CC
= +5.0V, T
A
= +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω, t
r
≤ 6 ns, and t
f
≤ 6 ns.
(3) C
L
includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
(5) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90C031B
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