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DEN

VODSEL

TRFB

REN

RRFB

RPWDNB

TCLK

TPWDNB

SERIALIZER ± DS90C241

PLL

Timing

and

Control

OUT

100

DESERIALIZER ± DS90C124

OUT

+ R

PLL

Timing

and

Control

OUT

LOCK

RCLK

Clock

Recovery

Output Latch

Serial to Parallel

DC Balance Decode

Input Latch

Parallel to Serial

DC Balance Encode

CLK1

bit0

bit1

bit2

bit3

bit4

bit5

bit

DCA

DCB

bit

CLK0

PRE

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90C124

DS90C241

SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017

DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit

FPD-Link II Serializer and Deserializer

1 Features

• 5-MHz to 35-MHz Clock Embedded and DC-

Balancing 24:1 and 1:24 Data Transmissions

• User Defined Pre-Emphasis Driving Ability

Through External Resistor on LVDS Outputs and

Capable to Drive Up to 10-Meter Shielded

Twisted-Pair Cable

• User-Selectable Clock Edge for Parallel Data on

Both Transmitter and Receiver

• Internal DC Balancing Encode and Decode

(Supports AC-Coupling Interface With No External

Coding Required)

• Individual Power-Down Controls for Both

Transmitter and Receiver

• Embedded Clock CDR (Clock and Data Recovery)

on Receiver and No External Source of Reference

Clock Required

• All Codes RDL (Random Data Lock) to Support

Live-Pluggable Applications

• LOCK Output Flag to Ensure Data Integrity at

Receiver Side

• Balanced T

SETUP

and T

HOLD

Between RCLK and

RDATA on Receiver Side

• PTO (Progressive Turnon) LVCMOS Outputs to

Reduce EMI and Minimize SSO Effects

• All LVCMOS Inputs and Control Pins Have

Internal Pulldown

• On-Chip Filters for PLLs on Transmitter and

Receiver

• Temperature Range: –40°C to 105°C

• Greater Than 8-kV HBM ESD Tolerant

• Meets AEC-Q100 Compliance

• Power Supply Range: 3.3 V ± 10%

• 48-Pin TQFP Package

2 Applications

• Automotive Central Information Displays

• Automotive Instrument Cluster Displays

• Automotive Heads-Up Displays

• Remote Camera-Based Driver Assistance

Systems

3 Description

The DS90C241 and DS90C124 chipset translates a

24-bit parallel bus into a fully transparent data and

control LVDS serial stream with embedded clock

information. This single serial stream simplifies

transferring a 24-bit bus over PCB traces or over

cable by eliminating the skew problems between

parallel data and clock paths. It saves system cost by

narrowing data paths, which in turn reduces PCB

layers, cable width, and connector size and pins.

The DS90C241 and DS90C124 incorporate LVDS

signaling on the high-speed I/O. LVDS provides a

low-power and low-noise environment for reliably

transferring data over a serial transmission path. By

optimizing the serializer output edge rate for the

operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost

signals over longer distances using lossy cables.

Internal DC balanced encoding and decoding

supports AC-coupled interconnects.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DS90C124

DS90C241

TQFP (48) 7.00 mm x 7.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Block Diagram

DS90C124

DS90C241

SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017

www.ti.com

Product Folder Links: DS90C124 DS90C241

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 7

6.1 Absolute Maximum Ratings ..................................... 7

6.2 ESD Ratings.............................................................. 7

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 8

6.5 Electrical Characteristics........................................... 8

6.6 Timing Requirements – Serializer............................. 9

6.7 Switching Characteristics – Serializer..................... 10

6.8 Switching Characteristics – Deserializer................. 10

6.9 Typical Characteristics............................................ 11

7 Parameter Measurement Information ................ 12

8 Detailed Description............................................ 17

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram ....................................... 17

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 20

9 Applications and Implementation ...................... 22

9.1 Application Information............................................ 22

9.2 Typical Application ................................................. 22

10 Power Supply Recommendations ..................... 27

11 Layout................................................................... 28

11.1 Layout Guidelines ................................................. 28

11.2 Layout Example .................................................... 29

12 Device and Documentation Support ................. 32

12.1 Documentation Support ........................................ 32

12.2 Related Links ........................................................ 32

12.3 Receiving Notification of Documentation Updates 32

12.4 Community Resources.......................................... 32

12.5 Trademarks........................................................... 32

12.6 Electrostatic Discharge Caution............................ 32

12.7 Glossary................................................................ 32

13 Mechanical, Packaging, and Orderable

Information ........................................................... 33

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision L (April 2013) to Revision M Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Deleted Lead temperature, soldering (260°C maximum) from Absolute Maximum Ratings.................................................. 7

• Added Thermal Information table ........................................................................................................................................... 8

• Added Typical Characteristics (PCLK = 5 MHz and PCLK = 25 MHz plus pre-emphasis).................................................. 11

Changes from Revision K (April 2013) to Revision L Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1

48DIN[19]

47DIN[18]

46DIN[17]

45DIN[16]

44DIN[15]

41DIN[14]

40DIN[13]

39DIN[12]

38DIN[11]

37DIN[10]

RESRVD

PT1

PT0

DEN

DOUT-

DOUT+

PRE

12VODSEL

11TRFB

10TCLK

9TPWDNB

8DCBOFF

5DCAOFF

4DIN[23]

3DIN[22]

2DIN[21]

1DIN[20]

DIN[0]

DIN[1]

DIN[2]

DIN[3]

DIN[4]

DIN[5]

DIN[6]

DIN[7]

DIN[8]

DIN[9]

DS90C241

48 PIN TQFP

DS90C124

DS90C241

www.ti.com

SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017

Product Folder Links: DS90C124 DS90C241

(1) G = Ground, I = Input, O = Output, P = Power

5 Pin Configuration and Functions

DS90C241 Serializer PFB Package

48-Pin TQFP

Top View

Pin Functions – DS90C241 Serializer

TYPE

(1)

DESCRIPTION

NAME NO.

LVCMOS PARALLEL INTERFACE PINS

DIN[23:0]

4-1, 48-44,

41-32, 29-25

I LVCMOS, Transmitter parallel interface data input pins. Tie LOW if unused, do not float.

TCLK 10 I

LVCMOS, Transmitter parallel interface clock input pin. Strobe edge set by TRFB

configuration pin.

CONTROL AND CONFIGURATION PINS

DCAOFF 5 I LVCMOS, Reserved. This pin must be tied LOW.

DCBOFF 8 I LVCMOS, Reserved. This pin must be tied LOW.

DEN 18 I

LVCMOS, Transmitter data enable.

DEN = H; LVDS driver outputs are enabled (ON).

DEN = L; LVDS driver outputs are disabled (OFF), Transmitter LVDS driver D

OUT

(±) outputs

are in TRI-STATE, PLL still operational and locked to TCLK.

PRE 23 I

LVCMOS, Pre-emphasis level select.

PRE = NC (No Connect); Pre-emphasis is disabled (OFF).

Pre-emphasis is active when input is tied to VSS through external resistor R

PRE

. Resistor

value determines pre-emphasis level. Recommended value R

PRE

≥ 3 kΩ; I

max

= [(1.2/R) ×

20], R

min

= 3 kΩ

RESRVD 13 I LVCMOS, Reserved. This pin must be tied LOW.

TPWDNB 9 I

LVCMOS, Transmitter power down bar.

TPWDNB = H; Transmitter is enabled and ON

TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS driver D

OUT

(±) outputs are

in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.

48REN

PR0

PR1

43RRFB

42RIN-

41RIN+

ROUT[15]

ROUT[14]

ROUT[13]

ROUT[12]

LOCK

RCLK

OR2

ROUT[11]

ROUT[10]

ROUT[9]

ROUT[8]

12ROUT[16]

11ROUT[17]

10ROUT[18]

9ROUT[19]

OR3

6ROUT[20]

5ROUT[21]

4ROUT[22]

3ROUT[23]

2RESRVD

1RPWDNB

ROUT[7]

ROUT[6]

ROUT[5]

ROUT[4]

OR1

ROUT[3]

ROUT[2]

ROUT[1]

ROUT[0]

DS90C124

48 PIN TQFP

PTO GROUP 3

PTO GROUP 1

PTO GROUP 2

DS90C124

DS90C241

www.ti.com

SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017

Product Folder Links: DS90C124 DS90C241

(1) G = Ground, I = Input, O = Output, P = Power

DS90C124 Deserializer PFB Package

48-Pin TQFP

Top View

Pin Functions – DS90C124 Deserializer

TYPE

(1)

DESCRIPTION

NAME NO.

LVCMOS PARALLEL INTERFACE PINS

RCLK 18 O LVCMOS, Parallel interface clock output pin. Strobe edge set by RRFB configuration pin.

ROUT[7:0] 25-28, 31-34 O LVCMOS, Receiver LVCMOS level outputs – Group 1

ROUT[15:8] 13-16, 21-24 O LVCMOS, Receiver LVCMOS level outputs – Group 2

ROUT[23:16] 3-6, 9-12 O LVCMOS, Receiver LVCMOS level outputs – Group 3

CONTROL AND CONFIGURATION PINS

REN 48 I

LVCMOS, Receiver data enable

REN = H; R

OUT

[23:0] and RCLK are enabled (ON).

REN = L; R

OUT

[23:0] and RCLK are disabled (OFF), receiver R

OUT

[23:0] and RCLK outputs

are in TRI-STATE, PLL still operational and locked to TCLK.

LOCK 17 O

LVCMOS, LOCK indicates the status of the receiver PLL

LOCK = H; receiver PLL is locked

LOCK = L; receiver PLL is unlocked, R

OUT

[23:0] and RCLK are TRI-STATED

RESRVD 2 I LVCMOS, Reserved. This pin must be tied LOW.

RPWDNB 1 I

LVCMOS, Receiver power down bar.

RPWDNB = H; Receiver is enabled and ON

RPWDNB = L; Receiver is in power down mode (Sleep), R

OUT

[23:0], RCLK, and LOCK are in

TRI-STATE standby mode, PLL is shutdown to minimize power consumption.

RRFB 43 I

LVCMOS, Receiver clock edge select pin.

RRFB = H; R

OUT

LVCMOS outputs strobed on the rising clock edge.

RRFB = L; R

OUT

LVCMOS outputs strobed on the falling clock edge.

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