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TI的DS90C387R是一款专为FPD-Link（Flat Panel Display Link）设计的发送器，用于在主机和数字显示接口之间传输像素数据。该器件旨在支持高达UXGA（Ultra eXtended Graphics Array）分辨率的显示器，并且能够与图形内存控制器集线器（GMCH）兼容。该发送器具有以下主要特性： 1. **Open LDI（Link Digital Interface）规范兼容**：DS90C387R遵循Open LDI标准，确保与各种显示面板的兼容性。 2. **频率支持**：它可以在25到85MHz的时钟频率范围内工作，为高分辨率显示提供必要的带宽。 3. **双12位双泵输入**：支持两种输入模式：一种是12位（双数据每时钟）输入，用于24位RGB，另一种是两个12位（双数据每时钟）输入，用于双24位RGB（总计48位）。数据在时钟的上升沿和下降沿都被采样。 4. **高数据传输速率**：在85MHz输入时钟和170Mbps输入数据速率下，每个LVDS线路的最大传输速率为595Mbps。这使得单个通道的总吞吐量可达2.38Gbps，而双通道则可达到4.76Gbps。 5. **预加重减少电缆负载效应**：通过预加重技术，DS90C387R能够在长距离、低成本电缆上保持信号完整性。 6. **DC平衡数据传输**：内置的DC平衡功能通过发射器减少ISI（ intersymbol interference，符号间干扰）失真。 7. **周期间抖动抑制**：发射器能有效地抑制周期间的抖动，确保信号质量稳定。 8. **低电压电平支持**：DS90C387R支持LVTTL和低电压电平输入（1.0到1.8V），适应不同的系统需求。 9. **两线串行通信接口**：该设备可以通过两线串行通信接口进行编程，最大通信速率可达400kHz，方便设置和控制。 10. **可编程输入时钟和控制 strobe**：用户可以根据需要配置输入时钟和控制信号，以适应不同应用场景。 11. **与DS90CF388接收器兼容**：DS90C387R的LVDS输出引脚布局与DS90C387相同，可以与DS90CF388接收器配对使用，构建完整的FPD-Link系统。 TI的DS90C387R是一个高性能、高灵活性的FPD-Link发送器，适用于需要高速、高质量视频传输的系统，如高清电视、专业显示器和嵌入式显示应用。其卓越的特性确保了在各种环境下的可靠性和稳定性。

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DS90C387R

www.ti.com

SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014

DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

Check for Samples: DS90C387R

FEATURES

DESCRIPTION

The DS90C387R transmitter is designed to support

• Complies with Open LDI Specification for

pixel data transmission from a Host to a Flat Panel

Digital Display Interfaces

Display up to UXGA resolution. It is designed to be

• 25 to 85MHz Clock Support

compatible with Graphics Memory Controller Hub

• Supports VGA through UXGA Panel

(GMCH) by implementing two data per clock and can

be controlled by a two-wire serial communication

Resolution

interface. Two input modes are supported: one port of

• Up to 4.76Gbps Bandwidth in Dual 24-bit RGB

12-bit( two data per clock) input for 24-bit RGB, and

In-to-Dual Pixel Out Application

two ports of 12-bit( two data per clock) input for dual

• Dual 12-bit Double Pumped Input DVO Port

24-bit RGB( 48-bit total). In both modes, input data

will be clocked on both rising and falling edges in

• Pre-Emphasis Reduces Cable Loading Effects

LVTTL level operation, or clocked on the cross over

• Drives Long, Low Cost Cables

of differential clock signals in the low swing operation.

• DC Balance Data Transmission Provided by

Each input data width will be 1/2 of clock cycle. With

Transmitter Reduces ISI Distortion

an input clock at 85MHz and input data at 170Mbps,

the maximum transmission rate of each LVDS line is

• Transmitter Rejects Cycle-to-Cycle Jitter (±2ns

595Mbps, for a aggregate throughput rate of

of Input Bit Period)

2.38Gbps/4.76Gbps. It converts 24/48 bits

• Support both LVTTL and Low Voltage Level

(Single/Dual Pixel 24-bit color) of data into 4/8 LVDS

Input (Capable of 1.0 to 1.8V)

(Low Voltage Differential Signaling) data streams.

• Two-Wire Serial Communication Interface up

DS90C387R can be programmed via the two-wire

to 400 KHz

serial communication interface. The LVDS output pin-

out is identical to DS90C387. Thus, this transmitter

• Programmable Input Clock and Control Strobe

can be paired up with DS90CF388, receiver of the

Select

112MHz LDI chipset or FPD-Link Receivers in non-

• Backward Compatible Configuration with

DC Balance mode operation which provides GUI/LCD

112MHz LDI and FPD-Link

panel/mother board vendors a wide choice of inter-

operation with LVDS based TFT panels.

• Optional Second LVDS Clock for Backward

Compatibility with FPD-Link Receivers

DS90C387R also comes with features that can be

• Compatible with TIA/EIA-644

found on DS90C387. Cable drive is enhanced with a

user selectable pre-emphasis feature that provides

additional output current during transitions to

counteract cable loading effects. DC Balancing on a

cycle-to-cycle basis is also provided to reduce ISI

(Inter-Symbol Interference), control signals (VSYNC,

HSYNC, DE) are sent during blanking intervals. With

pre-emphasis and DC Balancing, a low distortion eye-

pattern is provided at the receiver end of the cable.

These enhancements allow cables 5 to 15+ meters in

length to be driven depending on media characteristic

and pixel clock speed. Pre-emphasis is available in

both the DC Balanced and Non-DC Balanced modes.

In the Non-DC Balanced mode backward

compatibility with FPD-Link Receivers is obtained.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90C387R

www.ti.com

SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014

Absolute Maximum Ratings

(1)(2)

Min Max Unit

Supply Voltage (V

) −0.3 +4 V

LVCMOS/LVTTL Output Voltage −0.3 V

+ 0.3 V

LVDS Driver Output Voltage −0.3 V

+ 0.3

LVDS Output Short Circuit Duration Continuous

Junction Temperature +150 °C

Storage Temperature −65 +150 °C

Lead Temperature (Soldering, 4 seconds) +260 °C

Maximum Package Power Dissipation Capacity at 25°C 100 TQFP Package 2.8 W

Package Derating 18.2mW/°C above +25°C

HBM, 1.5kΩ, 100pF > 2 kV

ESD Rating

EIAJ, 0Ω, 200pF > 300 V

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to

imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

Recommended Operating Conditions

Min Nom Max Unit

All Supply Voltage 3.0 3.3 3.6 V

Operating Free Air Temperature (T

−10 +25 +70 °C

Supply Noise Voltage (V

) up to 33MHz 100 mV

p-p

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol Parameter Conditions Min Typ Max Unit

LVCMOS/LVTTL DC SPECIFICATIONS ( All pins, except output pins AnP, AnM, CLKnP and CLKnM, BAL, PD pins)

High Level Input Voltage V

REF

= V

CC3V

= V

2.0 V

Low Level Input Voltage V

REF

= V

CC3V

= V

GND 0.8 V

Input Clamp Voltage I

= 18 mA -0.8 -1.5 V

Input Current V

= 0.4V, or V

+1.8 +15 µA

= GND −15 0 µA

Low level Open Drain Output I

= 2 mA 0.1 0.3 V

Voltage

LVCMOS DC SPECIFICATIONS ( PD pin)

High Level Input Voltage V

REF

= V

CC3V

= V

2.9 V

Low Level Input Voltage V

REF

= V

CC3V

= V

GND 0.8 V

Input Clamp Voltage I

= 18 mA -0.8 -1.5 V

Input Current V

= 0.4V, or V

+1.8 +15 µA

= GND −15 0 µA

LVDS DRIVER DC SPECIFICATIONS (output pins AnP, AnM, CLKnP and CLKnM)

Differential Output Voltage R

= 100Ω 247 345 550 mV

ΔV

Change in V

between 35 mV

Complimentary Output States

Offset Voltage 1.125 1.25 1.475 V

ΔV

Change in V

between 35 mV

Complimentary Output States

Output Short Circuit Current V

OUT

= 0V, R

= 100Ω −3.5 −11 mA

Output TRI-STATE Current PD = 0V, V

OUT

= 0V or V

±1 ±10 µA

(1) Typical values are given for V

= 3.3V and T

= +25°C. Device tested in Non-Balanced mode only.

Product Folder Links: DS90C387R

DS90C387R

SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014

www.ti.com

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol Parameter Conditions Min Typ Max Unit

Low Voltage Mode DC SPECIFICATIONS( pins D0 to D23, CLKINP, CLKINM, DE, HSYNC,VSYNC)

IHLS

Low Swing High Level Input

(2)

REF

1.8 V

Voltage, V

= 3V +100mV

ILLS

Low Swing Low Level Input GND V

REF

- V

Voltage,V

= 3V 100mV

REF

Differential Input Reference Low Swing,V

REF

= ½V

DDQ

0.45 0.5*V

DDQ

1 V

Voltage, V

= 3V

TRANSMITTER SUPPLY CURRENT

ICCTW Transmitter Supply Current R

= 100Ω, f = 32.5 MHz, 115 180 mA

Worst Case C

= 5 pF, DUAL = V

Worst Case Pattern

f = 32.5 MHz, 75 mA

(Figure 4), BAL=High

DUAL = Gnd

(enabled),

f = 65 MHz, 150 215 mA

= 3.6V

DUAL = V

f = 65 MHz, 95 mA

DUAL = Gnd

f = 85 MHz, 175 235 mA

DUAL = V

f = 85 MHz, 110 mA

DUAL = Gnd

ICCTG Transmitter Supply Current, 16 R

= 100Ω, f = 32.5 MHz, 110 170 mA

Grayscale Case C

= 5 pF, DUAL = V

16 Grayscale Pattern

f = 32.5 MHz, 70 mA

(Figure 3), BAL =

DUAL = Gnd

High (enabled),

f = 65 MHz, 135 205 mA

= 3.6V

DUAL = V

f = 65 MHz, 90 mA

DUAL = Gnd

f = 85 MHz, 155 225 mA

DUAL = V

f = 85 MHz, 100 mA

DUAL = Gnd

ICCTZ Transmitter Supply Current, PD = Low 4.8 85 µA

Power Down Driver Outputs in TRI-STATE under

Powerdown Mode

(2) Low Swing DC threshold testing is preformed on data and control inputs only. Clock inputs tested by functional testing only.

DIGITAL DC CHARACTERISTICS for Two-Wire Serial Communication Interface

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Parameters list below only valid when I2CSEL pin = Vcc.

Symbol Parameter Conditions Min Typ Max Unit

(1) Logical “ 1 ” input voltage 2.1 V

(0) Logical “ 0 ” input voltage 0.8 V

Serial Bus Low level output voltage I

= 3mA 0.4 V

= 6mA 0.6 V

(1) Typical values are given for V

= 3.3V and T

= +25°C. Device tested in Non-Balanced mode only.

Product Folder Links: DS90C387R

DS90C387R

www.ti.com

SNLS062G –NOVEMBER 2000–REVISED JANUARY 2014

Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Device driving the transmitter

inputs should comply to this table of recommendations.

Symbol Parameter Min Typ Max Unit

TCIT TxCLK IN Transition Time (Figure 6) DUAL = Gnd or V

0.8 1.2 2.4 ns

TCIP TxCLK IN Period (Figure 7) DUAL = Gnd or V

11.76 T 40 ns

TCIH TxCLK in High Time (Figure 7) 0.4T 0.5T 0.6T ns

TCIL TxCLK in Low Time (Figure 7) 0.4T 0.5T 0.6T ns

VDDQ Low Swing Voltage Amplitude from GMCH 1.0 1.8 V

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol Parameter Min Typ Max Unit

LLHT LVDS Low-to-High Transition Time (Figure 5), PRE = no connect (minimum 0.14 0.9 ns

pre-empahsis).

LVDS Low-to-High Transition Time (Figure 5), PRE = V

(max. pre- 0.11 0.7 ns

empahsis).

LHLT LVDS High-to-Low Transition Time (Figure 5), PRE = no connect (mini. pre- 0.16 0.9 ns

empahsis).

LVDS High-to-Low Transition Time (Figure 5), PRE = V

(max. pre- 0.11 0.7 ns

empahsis).

TCCS TxOUT Channel to Channel Skew 100 ps

TPPOS0 Transmitter Output Pulse Position for Bit0 from f = 85MHz

(2)

-300 0 +300 ps

TxCLKout rising edge.

TPPOS1 Transmitter Output Pulse Position for Bit1 from 1.38 1.68 1.98 ns

TxCLKout rising edge.

TPPOS2 Transmitter Output Pulse Position for Bit2 from 3.06 3.36 3.66 ns

TxCLKout rising edge.

TPPOS3 Transmitter Output Pulse Position for Bit3 from 4.74 5.04 5.34 ns

TxCLKout rising edge.

TPPOS4 Transmitter Output Pulse Position for Bit4 from 6.42 6.72 7.02 ns

TxCLKout rising edge.

TPPOS5 Transmitter Output Pulse Position for Bit5 from 8.10 8.40 8.70 ns

TxCLKout rising edge.

TPPOS6 Transmitter Output Pulse Position for Bit6 from 9.78 10.08 10.38 ns

TxCLKout rising edge.

TSTC TxIN Setup to TxCLK IN in low swing mode at 85 MHz (Figure 8) 1.8 ns

THTC TxIN Hold to TxCLK IN in low swing mode at 85 MHz (Figure 8) 2 ns

TJCC Transmitter Jitter Cycle-to-cycle (Figure 13 f = 85 MHz 110 150 ps

Figure 14)

(3)

, DUAL = Gnd, V

= 3V

f = 65 MHz 80 120 ps

f = 32.5 MHz 75 115 ps

TPLLS Transmitter Phase Lock Loop Set (Figure 9) 10 ms

TPDD Transmitter Powerdown Delay (Figure 10) 100 ns

TPDL Transmitter Input to Output Latency (Figure 11) f = 32.5/65/85 MHz

(4)

1.5TCIP ns

+4.1

(1) Typical values are given for V

= 3.3V and T

= +25°C. Device tested in Non-Balanced mode only.

(2) The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT(process,

voltage and temperature) range.

(3) The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is

measured with a cycle-to-cycle jitter of ±2ns applied to the input clock signal while data inputs are switching (see Figure 13 and

Figure 14). A jitter event of 2ns, represents worse case jump in the clock edge from most graphics VGA chips currently available. This

parameter is used when calculating system margin as described in AN-1059.

(4) From V = 1.5V of CLKINP to V

DIFF

= 0V of CLK1P when R_FB = High, DUAL = Low or High, BAL = Low.

Product Folder Links: DS90C387R

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