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DS90C365A

www.ti.com

SNLS181I –APRIL 2004–REVISED APRIL 2013

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

Check for Samples: DS90C365A

FEATURES

DESCRIPTION

The DS90C365A is a pin to pin compatible

• Pin-to-pin compatible to DS90C363,

replacement for DS90C363, DS90C363A and

DS90C363A and DS90C365

DS90C365. The DS90C365A has additional features

• No special start-up sequence required

and improvements making it an ideal replacement for

between clock/data and /PD pins. Input signals

DS90C363, DS90C363A and DS90C365. family of

(clock and data) can be applied either before

LVDS Transmitters.

or after the device is powered.

The DS90C365A transmitter converts 21 bits of

• Support Spread Spectrum Clocking up to

LVCMOS/LVTTL data into four LVDS (Low Voltage

100kHz frequency modulation & deviations of

Differential Signaling) data streams. A phase-locked

±2.5% center spread or -5% down spread.

transmit clock is transmitted in parallel with the data

streams over the fourth LVDS link. Every cycle of the

• “Input Clock Detection” feature will pull all

transmit clock 21 bits RGB of input data are sampled

LVDS pairs to logic low when input clock is

and transmitted. At a transmit clock frequency of 87.5

missing and when /PD pin is logic high.

MHz, 21 bits of RGB data and 3 bits of LCD timing

• 18 to 87.5 MHz shift clock support

and control data (FPLINE, FPFRAME, DRDY) are

• Tx power consumption < 146 mW (typ) at 87.5

transmitted at a rate of 612.5 Mbps per LVDS data

channel. Using a 87.5 MHz clock, the data throughput

MHz Grayscale

is 229.687 Mbytes/sec. This transmitter can be

• Tx Power-down mode < 37 uW (typ)

programmed for Rising edge strobe or Falling edge

• Supports VGA, SVGA, XGA, SXGA (dual pixel),

strobe through a dedicated pin. A Rising edge or

SXGA+ (dual pixel), UXGA (dual pixel).

Falling edge strobe transmitter will interoperate with a

Falling edge strobe FPDLink Receiver without any

• Narrow bus reduces cable size and cost

translation logic.

• Up to 1.785 Gbps throughput

This chipset is an ideal means to solve EMI and

• Up to 223.125 Megabytes/sec bandwidth

cable size problems associated with wide, high-speed

• 345 mV (typ) swing LVDS devices for low EMI

TTL interfaces with added Spead Spectrum Clocking

• PLL requires no external components

support..

• Compliant to TIA/EIA-644 LVDS standard

• Low profile 48-lead TSSOP package

Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90C365A

SNLS181I –APRIL 2004–REVISED APRIL 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)

Supply Voltage (V

) −0.3V to +4V

CMOS/TTL Input Voltage −0.5V to (V

+ 0.3)V

LVDS Driver Output Voltage −0.3V to (V

+ 0.3)V

LVDS Output Short Circuit Duration Continuous

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Lead Temperature (Soldering, 4 seconds) +260°C

Maximum Package Power Dissipation Capacity at 25°C, TSSOP Package 1.98W

Package Derating 16 mW/°C above +25°C

HBM, 1.5kΩ, 100pF 7kV

ESD Rating

EIAJ, 0Ω, 200 pF 500V

Latch Up Tolerance at 25°C ±100mA

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply

that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Recommended Operating Conditions

Min Nom Max Unit

Supply Voltage (V

) 3.0 3.3 3.6 V

Operating Free Air Temperature (T

) −10 +25 +70 °C

Supply Noise Voltage (V

) 200 mV

TxCLKIN frequency 18 85 MHz

Electrical Characteristics

(1)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ

(2)

Max Unit

LVCMOS/LVTTL DC SPECIFICATIONS

High Level Input Voltage 2.0 V

Low Level Input Voltage 0 0.8 V

Input Clamp Voltage I

= −18 mA −0.79 −1.5 V

Input Current V

= 0.4V, 2.5V or V

+1.8 +10 μA

= GND −10 0 μA

LVDS DC SPECIFICATIONS

Differential Output Voltage R

= 100Ω 250 345 450 mV

ΔV

Change in V

between 35 mV

complimentary output states

Offset Voltage

(3)

1.13 1.25 1.38 V

ΔV

Change in V

between 35 mV

complimentary output states

Output Short Circuit Current V

OUT

= 0V, R

= 100Ω −3.5 −5 mA

Output TRI-STATE

Current Power Down = 0V, ±1 ±10 μA

OUT

= 0V or V

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

unless otherwise specified (except V

and ΔV

(2) Typical values are given for V

= 3.3V and T

= +25°C unless specified otherwise.

(3) V

previously referred as V

Product Folder Links: DS90C365A

DS90C365A

www.ti.com

SNLS181I –APRIL 2004–REVISED APRIL 2013

Electrical Characteristics

(1)

(continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ

(2)

Max Unit

TRANSMITTER SUPPLY CURRENT

ICCTW Transmitter Supply Current, R

= 100Ω, f = 25MHz 29 40 mA

Worst Case C

= 5 pF,

f = 40 MHz 34 45 mA

Worst Case Pattern

f = 65 MHz 42 55 mA

(Figure 1, Figure 3 )

"Typ" values are given

f = 87.5 MHz 48 60 mA

for V

= 3.6V and T

= +25°C, " Max " values

are given for V

3.6V and T

= −10°C

ICCTG Transmitter Supply Current, R

= 100Ω, f = 25 MHz 28 40 mA

16 Grayscale C

= 5 pF,

f = 40 MHz 32 45 mA

16 Grayscale Pattern

f = 65 MHz 39 50 mA

(Figure 2, Figure 3 )

"Typ" values are given

f = 87.5 MHz 44 56 mA

for V

= 3.6V and T

= +25°C, " Max " values

are given for V

3.6V and T

= −10°C

ICCTZ Transmitter Supply Current, Power Down = Low, 11 150 μA

Power Down Driver Outputs in TRI-STATE

under

Power Down Mode

Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Unit

TCIT TxCLK IN Transition Time (Figure 5) 1.0 6.0 ns

TCIP TxCLK IN Period (Figure 6) 11.76 T 50 ns

TCIH TxCLK IN High Time (Figure 6) 0.35T 0.5T 0.65T ns

TCIL TxCLK IN Low Time (Figure 6) 0.35T 0.5T 0.65T ns

TXIT TxIN , and /PD pin Transition Time 1.5 6.0 ns

TXPD Minimum pulse width for PWR DOWN pin signal 1 us

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Unit

LLHT LVDS Low-to-High Transition Time (Figure 4) 0.75 1.4 ns

LHLT LVDS High-to-Low Transition Time (Figure 4) 0.75 1.4 ns

TPPos0 Transmitter Output Pulse Position (Figure 12)

(1)

f = 25MHz −0.45 0 +0.45 ns

TPPos1 Transmitter Output Pulse Position 5.26 5.71 6.16 ns

TPPos2 Transmitter Output Pulse Position 10.98 11.43 11.88 ns

TPPos3 Transmitter Output Pulse Position 16.69 17.14 17.59 ns

TPPos4 Transmitter Output Pulse Position 22.41 22.86 23.31 ns

TPPos5 Transmitter Output Pulse Position 28.12 28.57 29.02 ns

TPPos6 Transmitter Output Pulse Position 33.84 34.29 34.74 ns

(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature

ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).

Product Folder Links: DS90C365A

DS90C365A

SNLS181I –APRIL 2004–REVISED APRIL 2013

www.ti.com

Transmitter Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Unit

TPPos0 Transmitter Output Pulse Position (Figure 12)

(1)

f = 40 MHz −0.25 0 +0.25 ns

TPPos1 Transmitter Output Pulse Position 3.32 3.57 3.82 ns

TPPos2 Transmitter Output Pulse Position 6.89 7.14 7.39 ns

TPPos3 Transmitter Output Pulse Position 10.46 10.71 10.96 ns

TPPos4 Transmitter Output Pulse Position 14.04 14.29 14.54 ns

TPPos5 Transmitter Output Pulse Position 17.61 17.86 18.11 ns

TPPos6 Transmitter Output Pulse Position 21.18 21.43 21.68 ns

TPPos0 Transmitter Output Pulse Position (Figure 12)

(1)

f = 65 MHz −0.20 0 +0.20 ns

TPPos1 Transmitter Output Pulse Position 2.00 2.20 2.40 ns

TPPos2 Transmitter Output Pulse Position for Bit 2 4.20 4.40 4.60 ns

TPPos3 Transmitter Output Pulse Position for Bit 3 6.39 6.59 6.79 ns

TPPos4 Transmitter Output Pulse Position 8.59 8.79 8.99 ns

TPPos5 Transmitter Output Pulse Position 10.79 10.99 11.19 ns

TPPos6 Transmitter Output Pulse Position 12.99 13.19 13.39 ns

TPPos0 Transmitter Output Pulse Position (Figure 12)

(1)

f = 87.5 MHz −0.20 0 +0.20 ns

TPPos1 Transmitter Output Pulse Position 1.48 1.68 1.88 ns

TPPos2 Transmitter Output Pulse Position 3.16 3.36 3.56 ns

TPPos3 Transmitter Output Pulse Position 4.84 5.04 5.24 ns

TPPos4 Transmitter Output Pulse Position 6.52 6.72 6.92 ns

TPPos5 Transmitter Output Pulse Position 8.20 8.40 8.60 ns

TPPos6 Transmitter Output Pulse Position 9.88 10.08 10.28 ns

TSTC Required TxIN Setup to TxCLK IN 2.5 ns

(Figure 6) at 85MHz

THTC Required TxIN Hold to TxCLK IN (Figure 6) at 0.5 ns

87.5 MHz

TCCD TxCLK IN to TxCLK OUT Delay. Measure from T

= −10°C, and 3.086 7.211 ns

TxCLK IN edge to immediatley crossing poing 85MHz for "Min" T

of differential TxCLK OUT by following the = 70°C, and

postive TxCLK OUT. 50% duty cycle input 25MHz for "Max",

clock is assumed. (Figure 7) V

= 3.6V, R_FB

pin = VCC

Measure from TxCLK IN edge to immediatley T

= −10°C, and 2.868 6.062 ns

crossing poing of differential TxCLK OUT by 85MHz for "Min" T

following the postive TxCLK OUT. 50% duty = 70°C, and

cycle input clock is assumed. (Figure 8) 25MHz for "Max",

= 3.6V, R_FB

pin = GND

SSCG Spread Spectrum Clock support; Modulation f = 25 MHz 100kHz ±

frequency with a linear profile.

(2)

2.5%/−5%

f = 40 MHz 100kHz ±

2.5%/−5%

f = 65 MHz 100kHz ±

2.5%/−5%

f = 87.5 MHz 100kHz ±

2.5%/−5%

TPLLS Transmitter Phase Lock Loop Set (Figure 9) 10 ms

TPDD Transmitter Power Down Delay (Figure 11) 100 ns

(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the

performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLKOUT− pins.

Product Folder Links: DS90C365A

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