TI-DS125MB203.pdf资源-CSDN文库

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DRIVE 1

EXPANDER

MB203

S_INA0

S_OUTA1

D_IN0

RXA_1

SEL0

SEL1

EXPANDER

D_IN1

S_OUTB1

S_INB0

S_INA1

S_OUTA0

S_OUTB0

D_OUT0

D_OUT1

RXA_0

TXA_1

TXA_0

RXB_1

RXB_0

TXB_1

TXB_0

DRIVE 0

VDD (2.5 V)

D_IN+

D_IN-

AD0

AD1

AD2

AD3

ENSMB

SCL

(2)

READ_EN / SEL1

SDA

(2)

S_OUTA+

S_OUTA-

GND (DAP)

(1) Schematic shows connection for SMBus Slave Mode (ENSMB = 1 k: to VIN)

For SMBus Master Mode or Pin Mode configuration, the connections are different.

(2) SMBus signals must be pulled up elsewhere in the system.

(3) Schematic requires different connections for 2.5 V mode.

(4) Schematic requires pullup resistor for 10G-KR Mode.

VIN

0.1F

(x5)

SMBus Slave

Mode

(1)

S_OUTB+

S_OUTB-

VDD_SEL

VIN (3.3 V)

D_OUT+

D_OUT-

S_INA+

S_INA-

S_INB+

S_INB-

Address straps

(pull-up to VIN or

pull-down to

GND)

(1)

1F

3.3V

(3)

10F

ALL_DONE

MODE

To SMBus/I2C

Host Controller

MB203

SMBus Slave Mode

(1)

SMBus Slave Mode

(1)

SATA/SAS

Mode

(4)

GND

RESET

1 OF 2

SEL0

SMBus Slave Mode

(1)

INPUT_EN

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS432

DS125MB203

ZHCSEN5C –OCTOBER 2012–REVISED DECEMBER 2015

DS125MB203 具具有有均均衡衡和和去去加加重重功功能能的的低低功功耗耗 12.5Gbps 双双通通道道

2:1/1:2 复复用用器器/缓缓冲冲器器

1 特特性性

• 12.5Gbps 双通道 2:1 复用器，1:2 开关或扇出

• 低至 390mW 的总功耗（典型值）

• 高级信号调节功能：

– 频率为 6.25GHz 时，最高可支持 30dB 的接收

均衡功能

– 发送去加重功能高达 –12dB

– 发送输出电压控制：600mV 至 1300mV

• 可通过引脚选择、电可擦可编程只读存储器

(EEPROM) 或 SMBus 接口进行编程

• 2.5V 或 3.3V 可选电源电压

• 运行温度范围：–40°C 至 +85°C

2 应应用用

• 10GE，10G-KR

• PCIe 1 代/2 代/3 代

• SAS2/SATA3（最高可达 6Gbps）

• XAUI，RXAUI

简简化化功功能能框框图图

3 说说明明

DS125MB203 器件是一款具有信号调节功能的双端口

2:1 复用器和 1:2 开关或扇出缓冲器，适用于数据传输

速率最高可达 12.5Gbps 的 10GE、10G-KR

(802.3ap)、光纤通道、PCIe、无线带宽、

SATA3/SAS2 和其他高速总线应用。接收器的连续时

间线性均衡器 (CTLE) 可提供必要的升压性能，从而在

12.5Gbps 的速率下对长达 30 英寸的 FR-4 或 8M 电

缆 (AWG-24) 进行补偿。该片上特性免除了对外部信

号调节器的需求。发送器具有可编程幅值电压等级，

可在 600 mVp-p 至 1300 mVp-p 范围内进行选择，同

时实现高达 12dB 的去加重。

DS125MB203 可配置为支持 PCIe、SAS/SATA、

10G-KR 或其他信号传输协议。在 10G-KR 和 PCIe 3

代模式下运行时，DS125MB203 以透明方式允许主机

控制器和端点优化完整链路并协商发送均衡器系数。这

种链路协商协议的无缝管理可确保系统级互操作性并最

大限度地降低延迟。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

DS125MB203 WQFN (54) 10.00mm x 5.50mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典典型型应应用用

DS125MB203

ZHCSEN5C –OCTOBER 2012–REVISED DECEMBER 2015

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 说说明明（（续续））.............................................................. 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 7

7.5 Electrical Characteristics........................................... 8

7.6 Electrical Characteristics – Serial Management Bus

Interface .................................................................. 10

7.7 Timing Requirements – Serial Bus Interface .......... 10

7.8 Typical Characteristics............................................ 12

8 Detailed Description............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 13

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 14

8.5 Programming .......................................................... 18

8.6 Register Maps......................................................... 19

9 Application and Implementation ........................ 40

9.1 Application Information............................................ 40

9.2 Typical Application .................................................. 41

10 Power Supply Recommendations ..................... 42

10.1 Power Supply Bypassing ...................................... 42

11 Layout................................................................... 44

11.1 Layout Guidelines ................................................. 44

11.2 Layout Example .................................................... 45

12 器器件件和和文文档档支支持持 ..................................................... 46

12.1 文档支持................................................................ 46

12.2 社区资源................................................................ 46

12.3 商标 ....................................................................... 46

12.4 静电放电警告......................................................... 46

12.5 Glossary................................................................ 46

13 机机械械、、封封装装和和可可订订购购信信息息....................................... 46

4 修修订订历历史史记记录录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (April 2013) to Revision C Page

• 已添加 ESD

额定值

表，

特性描述

部分，

器件功能模式

，

应用和实施

部分，

电源相关建议

部分，

布局

部分，

器件和文

档支持

部分以及

机械、封装和可订购信息

部分。 .................................................................................................................... 1

• Changed Signal detect pattern at 8 Gbps ............................................................................................................................. 8

Changes from Revision A (April 2013) to Revision B Page

• 已更改国家数据表的版面布局至 TI 格式................................................................................................................................ 1

DS125MB203

ZHCSEN5C –OCTOBER 2012–REVISED DECEMBER 2015

www.ti.com.cn

(1) LVCMOS inputs without the “Float ” conditions must be driven to a logic low or high at all times or operation is not ensured.

Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.

For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.

For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.

Pin Functions: Common Connections

(1)

TYPE DESCRIPTION

NAME NO.

DIFFERENTIAL HIGH-SPEED INPUTS AND OUTPUTS

D_IN0+,

D_IN0-,

D_IN1+,

D_IN1-

10, 11, 15, 16 I

Inverting and noninverting CML differential inputs to the equalizer. A gated on-chip 50-

Ω termination resistor connects D_INn+ to VDD and D_INn– to VDD when enabled. AC

coupling required on high-speed I/O.

D_OUT0+, D_

OUT0-,

D_OUT1+,

D_OUT1-

3, 4, 7, 8 O

Inverting and noninverting low power differential signaling 50-Ω outputs with de-

emphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on

high-speed I/O.

S_INA0+,

S_INA0-,

S_INA1+,

S_INA1-

45, 44, 40, 39 I

Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω

termination resistor connects S_INAn+ to VDD and S_INAn– to VDD. AC coupling

required on high-speed I/O.

S_INB0+,

S_INB0-,

S_INB1+,

S_INB1-

43, 42, 38, 37 I

Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω

termination resistor connects S_INBn+ to VDD and S_INBn– to VDD. AC coupling

required on high-speed I/O.

S_OUTA0+,

S_OUTA0-,

S_OUTA1+,

S_OUTA1-

35, 34, 31, 30 O

Inverting and noninverting low power differential signaling 50-Ω outputs with de-

emphasis. Fully compatible with AC-coupled CML inputs.

S_OUTB0+,

S_OUTB0-,

S_OUTB1+,

S_OUTB1-

33, 32, 29, 28 O

Inverting and noninverting low power differential signaling 50-Ω outputs with de-

emphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on

high-speed I/O.

CONTROL PINS - SHARED (LVCMOS)

ENSMB 48

I, FLOAT,

LVCMOS

System Management Bus (SMBus) enable pin

Tie 1 kΩ to VDD = register access SMBus slave mode

FLOAT = Read external EEPROM (master SMBUS mode)

Tie 1 kΩ to GND = pin mode

CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)

RESET 52 I, LVCMOS

0: Normal operation (device is enabled).

1: Low power mode.

VDD_SEL 25 I, FLOAT

Controls the internal regulator

FLOAT: 2.5-V mode

Tied to GND: 3.3-V mode

POWER

GND DAP Power Ground pad (DAP - die attach pad).

VDD

9, 14,36, 41,

Power

Power supply pins CML/analog

2.5-V mode, connect to 2.5V ± 5%

3.3-V mode, connect 0.1-µF cap to each VDD pin

VIN 24 Power

In 3.3-V mode, feed 3.3 V ±10% to VIN

In 2.5-V mode, leave floating.

DS125MB203

www.ti.com.cn

ZHCSEN5C –OCTOBER 2012–REVISED DECEMBER 2015

Pin Functions: SMBus/EEPROM Control

TYPE DESCRIPTION

NAME NO.

ENSMB = 1 (SMBUS SLAVE MODE), FLOAT (SMBUS MASTER MODE)

SCL 50

I, LVCMOS,

O, Open-

drain

ENSMB master or slave mode

SMBUS clock input pin is enabled (slave mode)

SMBUS clock output when loading configuration from EEPROM (master mode)

SDA 49

I, LVCMOS,

O, Open-

drain

ENSMB master or slave mode

The SMBus bidirectional SDA pin is enabled. Data input or open-drain (pulldown only)

output.

AD0-AD3

54, 53, 47,

I, LVCMOS

ENSMB Master or Slave mode

SMBus slave address inputs. In SMBus mode, these pins are the user set SMBus slave

address inputs.

READ_EN 26 I, LVCMOS

ENSMB = FLOAT (SMBUS master mode)

When using an external EEPROM, a transition from high to low starts the load from the

external EEPROM

CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)

MODE 21

I, 4-LEVEL,

LVCMOS

0: SATA/SAS, PCIe GEN 1/2 and 10GE

FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)

1: 10-KR

INPUT_EN 22

I, 4-LEVEL,

LVCMOS

0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see

SEL0/1 pin), input always enabled with 50 Ω.

20 kΩ to GND: Reserved

FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable,

FANOUT is disable

1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled

with 50 Ω.

SEL0 23

I, 4-LEVEL,

LVCMOS

Select pin for lane 0.

0: selects input S_INB0±, output S_OUTB0±.

20 kΩ to GND: Selects input S_INB0±, output S_OUTA0±.

FLOAT: selects input S_INA0±, output S_OUTB0±.

1: Selects input S_INA0±, output S_OUTA0±.

SEL1 26

I, 4-LEVEL,

LVCMOS

Select pin for lane 1.

0: Selects input S_INB1±, output S_OUTB1±.

20 kΩ to GND: Selects input S_INB1±, output S_OUTA1±.

FLOAT: Selects input S_INA1±, output S_OUTB1±.

1: Selects input S_INA1±, output S_OUTA1±.

OUTPUT (LVCMOS)

ALL_DONE 27 0, LVCMOS

Valid register load status output

0: External EEPROM load passed

1: External EEPROM load failed

剩余53页未读，继续阅读

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