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TI-TMDS171.pdf
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HDMI重定时器
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TMDS171
HDMI
Receiver
HDMI/DVI
Connector
IN_CLKp/n
OUT_CLKp/n
IN_D1p/n OUT_D1p/n
IN_D0p/n
OUT_D0p/n
OUT_D2p/nIN_D2p/n
3.3 V t 5 V
SDA_SRC
SCL_SRC
SDA_SNK
SCL_SNK
HPD_SRC HPD_SNK
SDA_CTL
SCL_CTL
3.3 V
TMDS RX
DDC
HPD
I
2
C
OE
VSADJ
3.3 V t 5 V
ARC_OUT SPDIF_IN
SPDIF
Copyright © 2016, Texas Instruments Incorporated
Interface
Unit
Audiovisual
Processing
Unit
HDMI
SW/HD
TMDS
171
Digital TV
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEN7
TMDS171, TMDS171I
ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017
TMDS171/I 3.4Gbps TMDS 重重定定时时器器
1
1 特特性性
1
• 高清多媒体接口 (HDMI) 输入端口与输出端口间具
有时钟和数据恢复 (CDR) 电路,支持高达
3.4Gbps 的数据传输速率
• 兼容 HDMI1.4b 电气参数。
• 支持 4k2k30p 和高达 WUXGA 12 位色深或
1080p,具有更高的刷新率™
• 对输入流重新定时以补偿随机抖动
• 自适应接收器均衡器或可编程固定均衡器
• I
2
C 和引脚设置可编程
• 5+ 位对内偏移补偿
• 包括眼图的链路调试工具,位于 RX 均衡器之后
• 支持单端模式 ARC
• 48 引脚 7mm x 7mm 0.5mm 间距超薄型四方扁平
无引线 (VQFN) 封装
• 扩展商业温度范围为 0°C 至 85°C (TMDS171)
• 工业温度范围为 -40℃ 至 85°C (TMDS171I)
2 应应用用
• 数字电视
• 数字投影仪
• 音频/视频设备
• 蓝光 (Blu-Ray) DVD
• 监视器
• 台式机/一体化计算机
• 有源线缆
3 说说明明
TMDS171 是一款数字视频接口 (DVI) 或高清多媒体接
口 (HDMI) 重定时器。TMDS171 支持四条 TMDS 通
道,音频返回通道 (SPDIF_IN/ARC_OUT)、热插拔检
测 (HPD) 和数字显示控制 (DDC) 接口。TMDS171 支
持高达 3.4Gbps 的信号传输速率,可实现最高分辨率
达 4k2k30p 24 位/像素和高达 WUXGA 12 位色深或
1080p,并且具有较高的刷新率。TMDS171 在低于
1Gbps 的数据速率下会自动配置为重驱动器,而在高
于该速率时会自动配置为重定时器。
TMDS171 支持双电源轨(VDD 为 1.2V,VCC 为
3.3V),有助于降低功耗。该器件采用多种电源管理
方法来降低整体功耗。TMDS171x 通过 I
2
C 或引脚设
置支持固定的 EQ 增益或自适应 EQ 控制,以补偿不
同长度的输入电缆或电路板走线。
器器件件信信息息
(1)
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
TMDS171
(VQFN) 48 引脚 7.00mm x 7.00mm
TMDS171I
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简简化化电电路路原原理理图图
2
TMDS171, TMDS171I
ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017
www.ti.com.cn
版权 © 2015–2017, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 4
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Switching Characteristics........................................ 10
6.7 Typical Characteristics............................................ 12
7 Parameter Measurement Information ................ 12
8 Detailed Description............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 28
8.5 Register Maps ........................................................ 30
9 Application and Implementation ........................ 43
9.1 Application Information............................................ 43
9.2 Source Side Application.......................................... 45
9.3 System Examples ................................................... 49
10 Power Supply Recommendations ..................... 50
11 Layout................................................................... 52
11.1 Layout Guidelines ................................................. 52
11.2 Layout Example .................................................... 53
12 器器件件和和文文档档支支持持 ..................................................... 54
12.1 相关文档 ........................................................... 54
12.2 接收文档更新通知 ................................................. 54
12.3 社区资源................................................................ 54
12.4 商标 ....................................................................... 54
12.5 静电放电警告......................................................... 54
12.6 Glossary................................................................ 54
13 机机械械、、封封装装和和可可订订购购信信息息....................................... 54
4 修修订订历历史史记记录录
Changes from Revision D (August 2016) to Revision E Page
• Added Note 3 to the Electrical Characteristics table .............................................................................................................. 8
• Deleted text "which is needed for certain HDMI CTS test." from the second paragraph in the Overview section .............. 20
• Changed section: Input Signal Detect Block ........................................................................................................................ 25
• Changed H to X in the first row of the HPD_SNK column in Table 36 ................................................................................ 51
• Changed the IN_Dx column in Table 36 .............................................................................................................................. 51
Changes from Revision C (April 2016) to Revision D Page
• Recommended Operating Conditions, Changed the CONTROL PINS section ..................................................................... 7
• Electrical Characteristics Changed the DDC and I2C section................................................................................................ 9
Changes from Revision B (February 2016) to Revision C Page
• Changed pin 36 Description From: TX_TERM_CTL = L: 150 - 300 Ω To: TX_TERM_CTL = L: Reserved in the Pin
Functions table ...................................................................................................................................................................... 6
• Added OE to V
IL
"Low-level input voltage" in the Recommended Operating Conditions table ............................................. 7
• Added OE to V
IH
"High-level input voltage" in the Recommended Operating Conditions table ............................................ 7
• Changed Figure 23 .............................................................................................................................................................. 22
• Deleted the VDD_ramp and VCC_ramp MIN values in Table 1 ......................................................................................... 23
• Changed TX_TERM_CTL = L to Reserved in Table 3 ........................................................................................................ 25
• Changed text "address 22h through the I
2
C interface" To: "address 0Bh through the I
2
C interface" DDC Functional
Description............................................................................................................................................................................ 29
• Added Note to 11–400-kbps in Table 8................................................................................................................................ 32
• Added Note to 11–400-kbps in Table 10.............................................................................................................................. 34
3
TMDS171, TMDS171I
www.ti.com.cn
ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017
Copyright © 2015–2017, Texas Instruments Incorporated
Changes from Revision A (December 2015) to Revision B Page
• Changed Pin 44 From: AUX_SRCn To: ARC_OUT Pin 45 From: AUX_SRCn To: SPDIF_IN in the Pin Configuration
and Functions image ............................................................................................................................................................. 4
Changes from Original (October 2015) to Revision A Page
• 已将器件状态从“产品预览”更改为“量产数据” .......................................................................................................................... 1
1
10
9
8
7
6
5
4
3
2
30
21
22
23
24
25
26
27
28
29
11
201918171615
14
13
12
40
31
32
33
34
35
36
3738
39
NC
VSADJ
HPD_SRC
SDA_SRC
SCL_SRC
GND
OUT_D0p
OUT_D0n
SDA_SNK
SCL_SNK
OE
VDD
VDD
TX_TERM_CTL
SCL_CTL
NC
SPDIF_IN
4142434445464748
GND
SIG_EN
VDD
ARC_OUT
I2C_EN/PIN
VDD
VCC
VDD
VCC
GND
HPD_SNK
PRE_SEL
EQ_SEL/A0
SDA_CTL
IN_D1n
IN_D1p
IN_D2n
IN_D2p
IN_D0n
IN_D0p
IN_CLKn
IN_CLKp
OUT_D2p
OUT_D2n
OUT_D1p
OUT_D1n
OUT_CLKp
OUT_CLKn
A1
SWAP/POL
GND
GND
4
TMDS171, TMDS171I
ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017
www.ti.com.cn
Copyright © 2015–2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
RGZ (QFN) Package
48 Pins
Top View
5
TMDS171, TMDS171I
www.ti.com.cn
ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017
Copyright © 2015–2017, Texas Instruments Incorporated
(1) (1) G = Ground, I = Input, O = Output, P = Power
(2) (H) Logic High (Pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (Pin strapped to GND through 65 kΩ resistor); (Mid-Level =
No connect)
Pin Functions
PIN
I/O
(1)
DESCRIPTION
NAME NO.
VCC 13, 43 P 3.3 V Power Supply
VDD 14, 23, 24, 37, 48 P 1.2 V Power Supply
GND 7, 19, 41, 30 G Ground
Thermal Pad G Ground
MAIN LINK INPUT PINS (FAIL SAFE)
IN_D2p/n 2, 3 I Channel 2 Differential Input
IN_D1p/n 5, 6 I Channel 1 Differential Input
IN_D0p/n 8, 9 I Channel 0 Differential Input
IN_CLKp/n 11, 12 I Clock Differential Input
MAIN LINK OUTPUT PINS (FAIL SAFE)
OUT_D2n/p 34, 35 O TMDS Data 2 Differential Output
OUT_D1n/p 31, 32 O TMDS Data 1 Differential Output
OUT_D0n/p 28, 29 O TMDS Data 0 Differential Output
OUT_CLKn/p 25, 26 O TMDS Clock Differential Output
HOT PLUG DETECT PINS
HPD_SRC 4 O Hot Plug Detect Output to source side
HPD_SNK 33 I Hot Plug Detect Input from sink side
AUDIO RETURN CHANNEL and DDC PINS
SPDIF_IN 45 I SPDIF signal input
ARC_OUT 44 O Audio return channel output
SDA_SRC 47 I/O Source Side TMDS Port Bidirectional DDC Data line
SCL_SRC 46 I/O Source Side TMDS Port Bidirectional DDC Clock line
SDA_SNK, 39 I/O Sink Side TMDS Port Bidirectional DDC Data Line
SCL_SNK 38 I/O Sink Side TMDS Port Bidirectional DDC Clock Line
CONTROL PINS
(2)
OE 42 I
Operation Enable/Reset Pin
OE = L: Power Down Mode
OE = H: Normal Operation
Internal weak pull up: Resets device when transitions from H to L
SIG_EN 17 I
Signal detector circuit enable
SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default)
SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby
Mode.
Internal weak pull down
PRE_SEL 20
I
3-Level
De-emphasis Control when I2C_EN/PIN = Low.
PRE_SEL = L: -2 dB
PRE_SEL = No Connect: 0 dB
PRE_SEL = H: Reserved
When I2C_EN/PIN = High; De-emphasis is controlled through I
2
C
EQ_SEL/A0 21 I
Input Receive Equalization pin strap when I2C_EN/PIN = Low
EQ_SEL = L: Fixed EQ at 7.5 dB
EQ_SEL = No Connect: Adaptive EQ
EQ_SEL = H: Fixed at 14 dB
When I2C_EN/PIN = High Address Bit 1
Note: 3 level for pin strap programming but 2 level when I
2
C address
I2C_EN/PIN 10 I
I2C_EN/PIN = High; Puts Device into I2C Control Mode
I2C_EN/PIN = Low; Puts Device into Pin Strap Mode
SCL_CTL 15 I/O
I
2
C Clock Signal when I
2
C_EN/PIN = High.
Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be
changed by I
2
C
SDA_CTL 16 I/O
I
2
C Data Signal when I
2
C_EN/PIN = High
Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be
changed by I
2
C
VSadj 22 I TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND
剩余62页未读,继续阅读
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