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HDMI转接驱动器
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TMDS
141
Interface
Unit
Audiovisual
Processing
Unit
HDMI
Rx
Digital TV
TMDS141
www.ti.com
SLLS737D –JUNE 2006– REVISED SEPTEMBER 2011
HDMI HIDER
Check for Samples: TMDS141
1
FEATURES
23
• Supports 2.25 Gbps Signaling Rate for up to
• 40-Pin QFN Package (RHA)
1080p Resolutions Supporting 36-bits Per
• ROHS Compatible and 260°C Reflow Rated
Pixel for Color Depth of 12-bits Per Color
• Accepts AC Couple DisplayPort Dual-Mode
• Compatible with HDMI 1.3a
Signals and Translates Them into a HDMI1.3a
• Integrated Receiver Termination Compatable TMDS Signal
• 8-dB Equalizer Compensates Losses from 5-m
APPLICATIONS
or Longer HDMI Cables
• Digital TV
• Selectable Output De-Emphasis Supports 1-m
HDMI Transmission
• DVD Player
• I
2
C™ Repeater Isolates Bus Capacitance at
• Set-Top-Box
Both Ends
• Audio Video Receiver
• High Impedance Outputs When Disabled
• Digital Projector
• TMDS Inputs HBM ESD Protection Exceeds
• DVI or HDMI cable
6 kV
• DisplayPort Level Translator
• 3.3-V Supply Operation
DESCRIPTION
The TMDS141 HDMI hider is designed to accommodate a 1-m HDMI cable between a HDMI connector and a
receiver. The internal cable causes signal distortion to high-speed TMDS signals, as well as increasing
capacitance to the DDC channel. Each TMDS141 contains four TMDS repeaters to transmit digital content with
signaling rates of up to 2.25-Gbps, and an I
2
C repeater to link extended display identification data (EDID) reading
and high-bandwidth digital content protection (HDCP) key exchange under I
2
C standard mode operations.
The device includes four TMDS compliant differential receivers with 50-Ω termination resistors and 3.3-V
termination voltage integrated at each receiver input pin. External terminations are not required. A built-in
frequency response equalization circuit, 8 dB at 825 MHz, compensates inter-symbol interference (ISI) losses
from a 5-m or longer input cable link.
The device also includes four TMDS compliant differential drivers. A precision resistor is connected externally
from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard.
A selectable de-emphasis circuit is available via the PRE input to drive long PCB traces or cables. When PRE is
high, the 3.5-dB high frequency gain offsets the losses due to the FR4 trace. PRE can be left open or kept low
when the de-emphasis function is not desired.
Figure 1. TYPICAL APPLICATION
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3I
2
C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
V
CC
R
INT
TMDS
Receiver
w/EQ
TMDS
Driver
TX2
TX2
RX2
RX2
TMDS
Receiver
w/EQ
TMDS
Driver
TX1
TX1
RX1
RX1
TMDS
Receiver
w/EQ
TMDS
Driver
TX0
TX0
RX0
RX0
TMDS
Receiver
w/EQ
TMDS
Driver
TXC
TXC
RXC
RXC
R
INT
R
INT
R
INT
V
CC
V
CC
V
CC
VSADJ
PRE
RSCL
RSDA
TSCL
TSDA
I2CEN
OE
OVS
TMDS141
SLLS737D –JUNE 2006–REVISED SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
With standard TMDS terminations at the outputs, all TMDS outputs are forced high-impedance when OE is set
high. The I
2
C repeater isolates the buses without accumulating the capacitance of both sides. It allows DDC
capacitance to be controlled under the desired load. The I
2
C outputs are high-impedance when device supply
voltage is less than 1.5 V or I2CEN is low. The OVS pin, output voltage select, provides the flexibility of adjusting
the output voltage level of the TSCL and TSDA side to optimize noise margins while interfacing to different HDMI
receivers. The device is characterized for operation from 0°C to 70°C.
FUNCTIONAL BLOCK DIAGRAM
2 Submit Documentation Feedback Copyright © 2006–2011, Texas Instruments Incorporated
Product Folder Link(s): TMDS141
VSADJ
RSCL
RSDA
V
CC
GND
OVS
V
CC
TSDA
TSCL
GND
GND
RXC
RXC
V
CC
RX0
RX0
GND
RX1
RX1
V
CC
Rx2
RX2
GND
V
CC
I2CEN
OE
PRE
GND
TX2
Tx2
GND
TXC
TXC
V
CC
TX0
TX0
GND
TX1
TX1
V
CC
1
2
3
4
5
6
7
8
9
10
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
30
29
28
27
26
25
24
23
22
21
TMDS141
www.ti.com
SLLS737D –JUNE 2006– REVISED SEPTEMBER 2011
RHA PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
RX2, RX1, RX0, RXC 1, 38, 35, 32 I TMDS Negative inputs
RX2, RX1, RX0, RXC 2, 39, 36, 33 I TMDS Positive inputs
TX2, TX1, TX0, TXC 10, 13, 16, 19 O TMDS Negative outputs
TX2, TX1, TX0, TXC 9, 12, 15, 18 O TMDS Positive outputs
RSCL 29 I/O DDC Bus clock line to source
RSDA 28 I/O DDC Bus data line to source
TSCL 22 I/O DDC Bus clock line to sink
TSDA 23 I/O DDC Bus data line to sink
VSADJ 30 I TMDS Compliant voltage swing control
I
2
C Repeater enable
I2CEN 5 I Low: High-Z
High: Active
OVS 25 I TSCL/TSDA Output voltage select
TMDS Output enable
OE 6 I Low: Active
High: High-Z
TMDS Output de-emphasis adjustment
PRE 7 I Low: 0 dB
High: 3.5 dB
4, 11, 17, 24, 27,
V
CC
Power supply
34, 40
3, 8, 14, 20, 21,
GND Ground
26, 31, 37
Copyright © 2006–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TMDS141
Z
TMDSOutputStage
Y
25W
25W
10mA
TMDSInputStage
A B
50W
50W
ControlInputStage
OVS
400W
ControlInputStage
PRE
OE
I2CEN
400W
T-SideI CInput/OutputStage
2
TSCL
TSDA
V
CC
400W
V
OL
R-SideI CInput/OutputStage
2
RSCL
RSDA
400W
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
TMDS141
SLLS737D –JUNE 2006–REVISED SEPTEMBER 2011
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
ORDERING INFORMATION
(1)
PART NUMBER PART MARKING PACKAGE
TMDS141RHAR TMDS141 40-PIN QFN Tape/Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
4 Submit Documentation Feedback Copyright © 2006–2011, Texas Instruments Incorporated
Product Folder Link(s): TMDS141
TMDS141
www.ti.com
SLLS737D –JUNE 2006– REVISED SEPTEMBER 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
Supply voltage range
(2)
–0.5 V to 4 V
RX, RX 2.0 V to 4 V
Voltage range TX, TX, PRE, VSADJ, OE, I2CEN, OVS, HPDn –0.5V to 4 V
RSCL, RSDA, TSCL, TSDA –0.5 V to 6 V
RX, RX ±6 kV
Human body model
(3)
All pins ±4 kV
Electrostatic
discharge
Charged-device model
(4)
(all pins) ±1500 V
Machine model
(5)
(all pins) ±200 V
Continuous power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
DERATING FACTOR
(1)
T
A
= 70°C
PACKAGE PCB JEDEC STANDARD T
A
≤ 25°C
ABOVE T
A
= 25°C POWER RATING
40-QFN RHA Low-K
(2)
839.7 mW 8.39 mW/°C 461.8 mW
40-QFN RHA High-K
(3)
3030.3 mW 30.3 mW/°C 1666.6mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
θJB
Junction-to-board thermal
30.96 °C/W
resistance
R
θJC
Junction- to-case thermal
32.42 °C/W
resistance
V
IH
= V
CC
, V
IL
= V
CC
- 0.5 V, R
T
= 50 Ω, PRE = Low 344 370
mW
V
CC
= AV
CC
= 3.3V, R
vsadj
= 4.64 kΩ
PRE = High 381 407
P
D
Device power dissipation
V
IH
= V
CC
, V
IL
= V
CC
- 0.6 V, R
T
= 50 Ω, PRE = Low 484
mW
V
CC
= 3.6 V, AV
CC
= 3.3V, R
vsadj
= 4.6 kΩ
PRE = High 526
Copyright © 2006–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TMDS141
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