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TI-TMDS341.pdf
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www.ti.com
FEATURES
APPLICATIONS
DESCRIPTION
TYPICAL APPLICATION
PC
TMDS
341
DVD Player
STB
Digital TV
or
Game
Machine
TMDS341
SLLS660B – AUGUST 2005 – REVISED JANUARY 2006
3-TO-1 DVI/HDMI SWITCH
• HBM ESD Protection Exceeds 3 kV
• Designed for Signaling Rates up to 1.65 Gbps • 3.3-V Supply Operation
in Support of UXGA Display
• 80-Pin TQFP Package
• Differential Interface Compatible with
• ROHS Compatible and 260 ° C Reflow Rated
Transition Minimized Differential Signaling
(TMDS) Electrical Specification
• Each Port Supports HDMI or DVI Inputs
• Switching From Three Digital-Video (DVI) or
Digital-Audio Visual (HDMI) Sources
• Isolated Digital Display Control (DDC) Bus for
• Digital TV
Unused Ports
• Digital Projector
• 5-V Tolerance to all DDC and HPD_SINK
• Audio Video Receiver
Inputs
• Integrated Receiver Termination
• Inter-Pair Output Skew < 100 ps
• 8-dB Receiver Equalization to Compensate for
5-m DVI Cable Losses
• High Impedance Outputs When Disabled
The TMDS341 is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that
allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug
detector, and an I
2
C interface are supported on each port. Each TMDS channel allows signaling rates up to 1.65
Gbps.
The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from
each port are switched through a 3-to-1 multiplexer. The I
2
C interface of the selected input port is linked to the
I
2
C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to
HPD_SINK. For the unused ports, the I
2
C interfaces are isolated, and the HPD pins are kept low.
Termination resistors (50- Ω ), pulled up to V
CC
, are integrated at each receiver input pin. External terminations are
not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential
output voltage to be compliant with the TMDS standard. When the output is connected to a standard TMDS
termination and OE is high, the output is high impedance.
The TMDS341 provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize
system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation
from 0 ° C to 70 ° C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
PRE
VSADJ
Y4
Z4
Y3
Z3
Y2
Z2
Y1
Z1
S1
S2
S3
HPD_SINK
SCL_SINK
SDA_SINK
SDA3
SCL3
SDA2
SCL2
SDA1
SCL1
HPD3
HPD2
HPD1
B31
A31
B32
A32
B33
A33
B34
A34
B21
A21
B22
A22
B23
A23
B24
A24
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Control Logic
3−to−1 MUX
TMDS
Drive
TMDS
Drive
TMDS
Drive
TMDS
Drive
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
V
CC
(3.3 V)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
(3.3 V)
V
CC
(3.3 V)
A11
B11
A12
B12
A13
B13
A14
B14
R
INT
R
INT
R
INT
R
INT
R
INT
R
INT
R
INT
R
INT
R
INT
R
INT
R
INT
R
INT
OE
TMDS341
SLLS660B – AUGUST 2005 – REVISED JANUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
2
www.ti.com
HPD2
SDA2
SCL2
GND
GND
B21
A21
B22
A22
GND
B23
A23
V
B24
A24
GND
HPD1
NC
O
E
HP D3
SDA
3
S C
L3
GND
B 31
A 31
B 32
A
32
GND
B
3
3
A
3
3
B
3
4
A 3
4
GND
N
C
HPD_SINK
SDA_SINK
SCL_SINK
GND
GND
Z1
Y1
Z2
Y2
GND
Z3
Y3
Z4
Y4
GND
S3
S2
S1
N C
P
R
E
V
G N D
A
1
4
B
1 4
A
1 3
B1 3
A
1
2
B1
2
A1
1
B1
1
G
N D
S
C L 1
S
D A
1
CC
V
CC
V
CC
V
CC
V
CC
V
CC
C
C
V
C
C
V
C C
V
C
C
VSADJ
2 3 4 5 6 7 8 9 10 11 12 131 14 15 16 17 18 19 20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
59 58 57 56 5560 54 52 51 5053 49 48 47 46 45 44 43 42 41
V
C
C
V
C
C
N C
G N D
TMDS341
SLLS660B – AUGUST 2005 – REVISED JANUARY 2006
PFC PACKAGE
(TOP VIEW)
3
www.ti.com
TMDS341
SLLS660B – AUGUST 2005 – REVISED JANUARY 2006
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
A11, A12, A13, A14 6, 9, 12, 15 I Port 1 TMDS positive inputs
A21, A22, A23, A24 68, 71, 74, 77 I Port 2 TMDS positive inputs
A31, A32, A33, A34 49, 52, 55, 58 I Port 3 TMDS positive inputs
B11, B12, B13, B14 5, 8, 11, 14 I Port 1 TMDS negative inputs
B21, B22, B23, B24 67, 70, 73, 76 I Port 2 TMDS negative inputs
B31, B32, B33, B34 48, 51, 54, 57 I Port 3 TMDS negative inputs
4, 10, 16 24, 30,
GND 36, 37, 47, 53, Ground
59, 65, 66, 72, 78
HPD1 80 O Port 1 hot plug detector output
HPD2 62 O Port 2 hot plug detector output
HPD3 44 O Port 3 hot plug detector output
Sink side hot plug detector input
HPD_SINK 40 I High: 5-V power signal asserted from source to sink and EDID is ready
Low: No 5-V power signal asserted from source to sink, or EDID is not ready
NC 1, 20, 41,60 No connect
OE 42 I Output enable, active low
Output de-emphasis adjustment
PRE 19 I High: 3 dB
Low: 0 dB
SCL1 3 I/O Port 1 DDC bus clock line
SCL2 64 I/O Port 2 DDC bus clock line
SCL3 46 I/O Port 3 DDC bus clock line
SCL_SINK 38 I/O Sink side DDC bus clock line
SDA1 2 I/O Port 1 DDC bus data line
SDA2 63 I/O Port 2 DDC bus data line
SDA3 45 I/O Port 3 DDC bus data line
SDA_SINK 39 I/O Sink side DDC bus data line
S1, S2, S3 21, 22, 23 I Source selector input
7, 13, 17 27, 33,
V
CC
43, 50, 56 61, 69, Power supply
75, 79
VSADJ 18 I TMDS compliant voltage swing control
Y1, Y2, Y3, Y4 34, 31, 28, 25 O TMDS positive outputs
Z1, Z2, Z3, Z4 35, 32, 29, 26 O TMDS negative outputs
4
www.ti.com
TMDS341
SLLS660B – AUGUST 2005 – REVISED JANUARY 2006
Table 1. Source Selection Lookup
(1)
CONTROL PINS I/O SELECTED HOT PLUG DETECT STATUS
SCL_SINK
S1 S2 S3 Y/Z HPD1 HPD2 HPD3
SDA_SINK
SCL1
H x x A1/B1 HPD_SINK L L
SDA1
SCL2
L H x A2/B2 L HPD_SINK L
SDA2
SCL3
L L H A3/B3 L L HPD_SINK
SDA3
L L L None (Z) None (Z) L L L
(1) H: Logic high; L: Logic low; X: Don't care; Z: High impedance
5
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