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TI-SN75DP129.pdf
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DP转TMDS
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1
FEATURES APPLICATIONS
DESCRIPTION
SN75DP129
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
www.ti.com
DisplayPort to TMDS Translator
• Personal Computer Market
• DisplayPort Physical Layer Input Port to TMDS
Physical Layer Output Port
– DP/TMDS Hardware Key (Dongle)
– Desktop PC
• Integrated TMDS Level Translator With
Receiver Equalization
– Notebook PC
– Docking Station
• Supports Data Rates up to 2.5 Gbps
– Standalone Video Card
• Integrated I
2
C Logic Block for DVI / HDMI
Connector Recognition
• Integrated Active I
2
C Buffer
• Enhanced ESD: 12 kV on all Pins
• Enhanced Commercial Temperature Range:
0 ° C to 85 ° C
• 36 Pin 6 × 6 QFN Package
The SN75DP129 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output.
The TMDS output has a built-in level translator, compliant with Digital Visual Interface 1.0 (DVI) and High
Definition Multimedia Interface 1.3 (HDMI) standards. The SN75DP129 is specified up to a maximum data rate of
2.5 Gbps, supporting resolutions greater then 1920 x 1200 or HDTV 12-bit color depth at 1080p (progressive
scan).
An integrated Active I
2
C buffer isolates the capacitive loading of the source system from that of the sink and
interconnecting cable. This isolation improves overall signal integrity of the system and provides greater design
margin within the source system for DVI / HDMI compliance testing.
A logic block was designed into the SN75DP129 to assist with TMDS connector identification. Through the use of
the I
2
C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally
supporting HDMI content.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
TYPICAL APPLICATION
Dongle
Computer Notebook
DockingStation
GPU
SN75DP129
TMDSBuffer
DVIorHDMI
Compliant
MonitororHDTV
DP++
TMDS
SN75DP129
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
GPU — Graphics Processing Unit
DP++ — Dual-Mode DisplayPort
TMDS — Transition-Minimized Differential Signaling
DVI — Digital Visual Interface
HDMI — High Definition Multimedia Interface
2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
www.ti.com
INTERNAL DATA CONNECTION DIAGRAM
GND
LP
TMDS_2(n)
VSadj
SDA
SCL
HPD_IN
VDD
HPD_OUT
GND
VCC
ML_IN0(p)
I
2
C_EN
VCC
I
2
C
Slave
TMDS_2(p)
ML_IN0(n)
ML_IN1(p)
ML_IN1(n)
VCC
ML_IN2(p)
ML_IN2(n)
GND
ML_IN3(p)
ML_IN3(n)
VCC
GND
TMDS_CLK(n)
TMDS_CLK(p)
VCC
TMDS_0(n)
TMDS_0(p)
GND
TMDS_1(n)
TMDS_1(p)
SN75DP129
AUX_I C(p)
2
1
AUX_I C(n)
2
1
SN75DP129
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
(1) I
2
C bus data (n-SDA) and clock (p-SCL) lines.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN75DP129
www.ti.com
PIN CONFIGURATION
1
I
2
C_EN
VDD
ML_IN0(p)
HPD_OUT
SDA
VSadj
VCC
TMDS_2(n)
SCL
2 3 4 5 6 7 8
11
10
12
13
14
15
16
17
35
36
34
33
32
31
30
29
2627 24 23 22 21 2025
9
18
19
28
GND
VCC
LP
TMDS_2(p)
ML_IN0(n)
ML_IN1(p)
ML_IN1(n)
VCC
ML_IN2(p)
ML_IN2(n)
GND
ML_IN3(p)
ML_IN3(n)
VCC
GND
HPD_IN
GND
TMDS_CLK(n)
TMDS_CLK(p)
VCC
TMDS_0(n)
TMDS_0(p)
GND
TMDS_1(n)
TMDS_1(p)
SN75DP129
RHHPACKAGE
(TopView)
AUX_I
2
C(p)
1
AUX_I
2
C(n)
1
SN75DP129
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
(1) I
2
C bus data (n-SDA) and clock (p-SCL) lines.
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION TYPE
NAME NO.
(1)
AUX_I
2
C
(2)
11(p), 12(n) I/O Source Side Bidirectional DisplayPort Auxiliary Data Line DDC LINK (Source)
GND 6, 10, 19, 25, 36 Ground Ground
HPD_IN 15 I Hot Plug Detect (HPD) Input Hot Plug Detect
HPD_OUT 13 O Hot Plug Detect (HPD) Output Hot Plug Detect
Internal I
2
C register enable, used for HDMI / DVI connector
I
2
C_EN 32 I Control
differentiation
LP 33 I Low Power Select Bar Control
ML_IN 0 34(p), 35(n) I DisplayPort Main Link Channel 0 Differential Input Main Link Input Pins
ML_IN 1 1(p), 2(n) I DisplayPort Main Link Channel 1 Differential Input Main Link Input Pins
ML_IN 2 4(p), 5(n) I DisplayPort Main Link Channel 2 Differential Input Main Link Input Pins
ML_IN 3 7(p), 8(n) I DisplayPort Main Link Channel 3 Differential Input Main Link Input Pins
TMDS_2 30(p), 29(n) O TMDS Data 2 Differential Output Main Link Output
TMDS_1 27(p), 26(n) O TMDS Data 1 Differential Output Main Link Output
TMDS_0 24(p), 23(n) O TMDS Data 0 Differential Output Main Link Output
TMDS_CLK 21(p), 20(n) O TMDS Data Clock Differential Output Main Link Output
SCL 17 I/O TMDS Port Bidirectional I
2
C Clock Line DDC Link (Sink)
SDA 16 I/O TMDS Port Bidirectional I
2
C Data Line DDC Link (Sink)
VCC 3, 9, 18, 22, 28 3.3 V Supply Voltage Supply
(1) (p) Positive; (n) Negative
(2) I
2
C bus data (n-SDA) and clock (p-SCL) lines.
4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
www.ti.com
Input/Output Equivalent Circuits
+
–
V
CC
50 W 50 W
V
TERM
V
TERM
Z
Y
10mA
SN75DP129
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTION TYPE
NAME NO.
(1)
VDD 14 HPD Supply Voltage Supply
VSadj 31 I TMDS-Compliant Voltage Swing Control Reference
Figure 1. DisplayPort Input Stage
Figure 2. TMDS Output Stage
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN75DP129
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