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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSES6

SN65DP141

ZHCSEQ7 –FEBRUARY 2016

SN65DP141 DisplayPort 线线性性转转接接驱驱动动器器

1

1 特特性性

1

• 支持 VESA DisplayPort 1.3 和 eDP 1.4

• 四通道线性转接驱动器，最高支持 12Gbps 的数据

速率，包括 DisplayPort RBR、HBR、HBR2 和

HBR3

• 与协议无关

• 对 DP 链路协商透明

• 与在链路上的位置无关，适用于源设备、接收设备

和电缆应用

• 6GHz 时的 15dB 模拟均衡

• 输出线性动态范围：1200mV

• 带宽：> 20GHz

• 6GHz 时的回波损耗优于 16dB

• 2.5V 或 3.3V ±5% 单电源选项

• 低功耗，2.5V V

CC

时每通道 80mW

• 通用输入输出接口 (GPIO) 或者 I

2

C 控制

2 应应用用

• 平板电脑

• 笔记本电脑

• 台式机

• 扩展坞

3 说说明明

SN65DP141 是一款与协议无关的异步、低延迟、四通

道线性均衡器，该器件经过优化适用于高达 12Gbps

的数据速率并且可对电路板走线和电缆所产生的损耗进

行补偿。

该器件对 DisplayPort (DP) 链路协商透明，这使得 DP

源设备和接收设备能够执行有效的链路协商，克服了传

统“aux snooping”转接驱动器的缺点。此外，该器件与

位置无关。它可置于源设备、电缆或接收设备内，从而

为总体链路预算有效提供“负损耗”分量。SN65DP141

内的线性均衡在与接收器搭配使用时还可提高链路裕

度，从而实现判决反馈均衡 (DFE)。

SN65DP141 支持采用 I

2

C 和 GPIO 配置对均衡、增

益、动态范围进行独立通道控制。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

SN65DP141 WQFN (38) 7.00mm x 5.00mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

空白

简简化化电电路路原原理理图图

2

SN65DP141

ZHCSEQ7 –FEBRUARY 2016

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information ................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 7

6.7 Switching Characteristics, I

2

C Interface.................... 7

6.8 Typical Characteristics.............................................. 8

7 Parameter Measurement Information .................. 9

8 Detailed Description............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 13

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 15

8.5 Register Maps ........................................................ 17

9 Application and Implementation ........................ 23

9.1 Application Information............................................ 23

9.2 Typical Application ................................................. 23

10 Power Supply Recommendations ..................... 25

11 Layout................................................................... 26

11.1 Layout Guidelines ................................................. 26

11.2 Layout Example .................................................... 27

12 器器件件和和文文档档支支持持 ..................................................... 28

12.1 社区资源................................................................ 28

12.2 商标 ....................................................................... 28

12.3 静电放电警告......................................................... 28

12.4 Glossary................................................................ 28

13 机机械械、、封封装装和和可可订订购购信信息息....................................... 28

4 修修订订历历史史记记录录

日日期期修修订订版版本本注注释释

2016 年2 月 * 首次发布。

4

SN65DP141

ZHCSEQ7 –FEBRUARY 2016

www.ti.com.cn

Pin Functions (continued)

I/O DESCRIPTION

NAME NO.

CONTROL SIGNALS

SDA 14 I/O (open drain)

GPIO mode:

No action needed.

I

2

C mode:

I

2

C data. Connect a 10-kΩ pull-up resistor

externally.

DRV_PK#/SCL 15

I

(with 200-kΩ internal

pull-up)

GPIO mode:

HIGH: disable Driver peaking

LOW: enables Driver 6-dB AC peaking

I

2

C mode:

I

2

C CLK. Connect a 10-kΩ pull-up resistor

externally.

I2C_EN 16

I

(with 200-kΩ internal

pull-up)

Configures the device operation for I

2

C or GPIO mode:

HIGH: enables I2C mode

LOW: enables GPIO mode

TX_DC_GAIN/CS 17

I

(with 200-kΩ Internal

pull-down, 2.5V/3.3V

CMOS)

GPIO mode:

HIGH: 6 dB DC gain for transmitter

LOW: 0 dB DC gain for transmitter

I

2

C mode:

HIGH: acts as Chip Select

LOW: disables I

2

C interface

REXT 18 I (analog) External Bias Resistor: 1,200 Ω to GND

EQ0/ADD0 33

I

(2.5V/3.3V CMOS -

3-state)

GPIO mode:

Working with RX_GAIN and EQ1 to determine the

receiver DC and AC gain.

I

2

C mode:

ADD0 along with pins ADD1 and ADD2

comprise the three bits of I

2

C slave

address. ADD2:ADD1:ADD0:XXX

EQ_MODE/ ADD2 35

I

(with 200-kΩ Internal

pull-down, 2.5V/3.3V

CMOS )

GPIO mode:

HIGH: Trace mode

LOW: Cable mode

I

2

C mode:

ADD2 along with pins ADD1 and ADD0

comprise the three bits of I

2

C slave

address. ADD2:ADD1:ADD0:XXX

RX_GAIN 36

I

(2.5V/3.3V CMOS -

3-state)

GPIO mode:

Working with EQ0 and EQ1 to determine the

receiver DC and AC gain.

I

2

C mode:

No action needed

PWD# 37

I

(with 200-kΩ Internal

pull-up, 2.5V/3.3V

CMOS)

HIGH: Normal Operation

LOW: Power downs the device, inputs off and outputs disabled, resets I

2

C

EQ1/ADD1 34

I

(2.5V/3.3V CMOS -

3-state)

GPIO mode:

Working with RX_GAIN and EQ0 to determine the

receiver DC and AC gain.

I

2

C mode:

ADD1 along with pins ADD0 and ADD2

comprise the three bits of I

2

C slave

address ADD2:ADD1:ADD0:XXX

POWER SUPPLY

VCC

3, 6, 7, 10, 13,

19, 22, 25, 26,

29, 32, 38

Power Power supply 2.5V ±5%, 3.3V ±5%

GND Center Pad Ground

The ground center pad is the metal contact at the bottom of the package. This pad must be

connected to the GND plane. At least 15 PCB vias are recommended to minimize inductance

and provide a solid ground. Refer to the package drawing (RLJ-package) for the via placement.

5

SN65DP141

www.ti.com.cn

ZHCSEQ7 –FEBRUARY 2016

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN MAX UNIT

Supply voltage range VCC –0.3 4 V

Differential voltage between INx_P and INx_N VIN, DIFF –2.5 2.5 V

Voltage at INx_P and INx_N, VIN+, IN– –0.5 V

CC

+ 0.5 V

Voltage on control IO pins,V

IO

–0.5 V

CC

+ 0.5 V

Continuous current at high speed differential data

inputs(differential)

IN+, IN– –25 25 mA

Continuous current at high speed differential data

outputs

IOUT+, IOUT– –25 25 mA

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .

6.2 ESD Ratings

VALUE UNIT

V

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±2000

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101

(2)

±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

DR Operating data rate 12 Gbps

V

CC

Supply voltage 2.375 2.5/3.3 3.465 V

T

C

Junction temperature –10 125 °C

T

A

Operating free-air temperature –40 85 °C

CMOS DC SPECIFICATIONS

V

IH

Input high voltage 0.8 x V

CC

V

(MID)

Input middle voltage V

CC

x 0.4 V

CC

x 0.6 V

V

IL

Input low voltage –0.5 0.2 x V

CC

V

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.4 Thermal Information

THERMAL METRIC

(1)

SN65DP141

UNITRLJ (WQFN)

38 PINS

R

θJA

Junction-to-ambient thermal resistance 36.9 °C/W

R

θJC(top)

Junction-to-case (top) thermal resistance 22.3 °C/W

R

θJB

Junction-to-board thermal resistance 10.7 °C/W

ψ

JT

Junction-to-top characterization parameter 0.3 °C/W

ψ

JB

Junction-to-board characterization parameter 10.6 °C/W

R

θJC(bot)

Junction-to-case (bottom) thermal resistance 1.9 °C/W

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