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TI-LMK04610.pdf
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DAC
Recovered
³GLUW\´FORFNRU
clean clock
0XOWLSOH³FOHDQ´
clocks at different
frequencies
CLKout1 &
CLKout2
CLKout9
FPGA
CLKin0
VCXO
Backup
Reference
Clock
CLKin1
OSCout
DAC
CLKout3 &
CLKout4
ADC
LMX2582
PLL+VCO
CLKout10
CLKout7 &
CLKout8
CLKout5 &
CLKout6
LMK04610
Copyright © 2017, Texas Instruments Incorporated
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本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS699
LMK04610
ZHCSG17B –JANUARY 2017–REVISED JULY 2019
具具有有双双环环路路 PLL 且且符符合合 JESD204B 标标准准的的 LMK04610 超超低低噪噪声声和和低低功功耗耗
时时钟钟抖抖动动消消除除器器
1
1 特特性性
1
• 双环路 PLL 架构
• 超低噪声（10kHz 至 20MHz）：
– 1966.08MHz 频率下 48fs RMS 抖动
– 983.04MHz 频率下 50fs RMS 抖动
– 122.88MHz 频率下 61fs RMS 抖动
• 122.88MHz 时具有 –165dBc/Hz 本底噪声
• JESD204B 支持
– 一次性、脉冲和连续 SYSREF
• 10 个差动输出时钟（处于 8 个频率组中）
– 介于 700mVpp 和 1600mVpp 之间的可编程输
出摆幅
– 每个输出对可配置为 SYSREF 时钟输出
– 16 位通道分频器
– 最小 SYSREF 频率为 25kHz
– 最大输出频率为 2GHz
– 精密数字延迟，动态可调
– 数字延迟 (DDLY) ½ × 时钟分配路径频率
（最大 2GHz）
– 60ps 步长模拟延迟
– 50% 占空比输出分配，1 至 65535
（偶数和奇数）
• 2 个基准输入
– 输入丢失时采用保持模式
– 自动和手动切换模式
– 信号损失 (LOS) 检测
• 在 10 个有源输出下的典型功耗为 0.88W
• 通常由 1.8V（输出、输入）和 3.3V 电源（数字、
PLL1、PLL2_OSC、PLL2 内核）供电
• 完全集成的可编程环路滤波器
• PLL2
– PLL2 相位检测器频率高达 250MHz
– OSCin 倍频器
– 集成式低噪声 VCO
• 内部功率调节：优于 –80dBc PSRR（在 VDDO
上）（对于 122.88MHz 差动输出）
• 3 线制或 4 线制 SPI 接口（4 线制为默认设置）
• –40ºC 至 +85ºC 工业环境温度
• 支持 105ºC PCB 温度（在散热焊盘上测量）
• LMK04610：8mm × 8mm VQFN-56 封装，间距为
0.5mm
2 应应用用
• LTE-BTS、小型蜂窝、远程射频单元 (RRU) 等无
线基础设施
• 数据转换器和集成收发器时钟
• 网络、SONET/SDH、DSLAM
• 测试和测量
3 说说明明
LMK0461x 器件系列具有业界性能最高且功耗最低的
抖动清除器，支持 JESD204B 接口。
器器件件信信息息
(1)
器器件件型型号号 VCO 频频率率
LMK04610 5870MHz 至 6175MHz
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简简化化原原理理图图
2
LMK04610
ZHCSG17B –JANUARY 2017–REVISED JULY 2019
www.ti.com.cn
版权 © 2017–2019, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions......................... 5
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Digital Input and Output Characteristics (CLKin_SEL,
STATUSx, SYNC, RESETN) ..................................... 9
7.6 Clock Input Characteristics (CLKinX)........................ 9
7.7 Clock Input Characteristics (OSCin) ....................... 10
7.8 PLL1 Specification Characteristics ......................... 11
7.9 PLL2 Specification Characteristics ......................... 11
7.10 Clock Output Type Characteristics (CLKoutX)...... 12
7.11 Oscillator Output Characteristics (OSCout) .......... 13
7.12 Jitter and Phase Noise Characteristics for CLKoutX
and OSCout ............................................................. 14
7.13 Clock Output Skew and Isolation Characteristics . 15
7.14 Clock Output Delay Characteristics ...................... 15
7.15 DEFAULT POWER on RESET CLOCK OUTPUT
Characteristics ......................................................... 15
7.16 Power Supply Characteristics ............................... 16
7.17 Typical Power Supply Noise Rejection
Characteristics ......................................................... 16
7.18 SPI Interface Timing ............................................. 17
7.19 Timing Diagram..................................................... 17
7.20 Typical Characteristics.......................................... 18
8 Parameter Measurement Information ................ 20
8.1 Differential Voltage Measurement Terminology ..... 20
8.2 Output Termination Scheme ................................... 20
9 Detailed Description............................................ 22
9.1 Overview ................................................................. 22
9.2 Functional Block Diagram ....................................... 24
9.3 Feature Description................................................. 25
9.4 Device Functional Modes........................................ 52
9.5 Programming........................................................... 54
9.6 Register Maps......................................................... 56
10 Application and Implementation...................... 116
10.1 Application Information........................................ 116
10.2 Typical Application .............................................. 117
10.3 Do's and Don'ts................................................... 119
11 Power Supply Recommendations ................... 120
11.1 Recommended Power Supply Connection ......... 120
11.2 Current Consumption / Power Dissipation
Calculations............................................................ 120
12 Layout................................................................. 121
12.1 Layout Guidelines ............................................... 121
12.2 Layout Example .................................................. 122
13 器器件件和和文文档档支支持持 ................................................... 123
13.1 器件支持 ............................................................. 123
13.2 接收文档更新通知 ............................................... 123
13.3 社区资源.............................................................. 123
13.4 商标 ..................................................................... 123
13.5 静电放电警告....................................................... 123
13.6 Glossary.............................................................. 123
14 机机械械、、封封装装和和可可订订购购信信息息..................................... 123
4 修修订订历历史史记记录录
Changes from Revision A (June 2017) to Revision B Page
• 删除了
双环路
PLL
架构
特性要点下的项目列表 ..................................................................................................................... 1
• 添加了
超低噪声
特性要点 ....................................................................................................................................................... 1
• 将 VCO 频率单位从“5.8GHz 至 6.175GHz”更改为“5870MHz 至 6175MHz” .......................................................................... 1
• Added LMK04616 device configuration information............................................................................................................... 4
• Changed VCO frequency from: 5800 MHz to: 5870 MHz ...................................................................................................... 4
• Added PACKAGE column to device configuration information table ..................................................................................... 4
• Added LMK04616 row to device configuration information table ........................................................................................... 4
• Added Footnote and link to LMK04616 datasheet ................................................................................................................ 4
• Added OSCout polarity information to the OSCout/OSCout* pin description ........................................................................ 6
• Changed PLL1 phase detector maximum frequency from 40 MHz to 4 MHz ..................................................................... 11
• Changed VCO tuning range minimum from: 5800 to: 5870 ................................................................................................. 11
• Changed V
OD
symbol to V
OD,pp
to match mVpp units. .......................................................................................................... 12
• Changed V
OD
symbol to V
OD,pp
to match mVpp units. ......................................................................................................... 13
• Added content to the HSDS 4/6/8mA section ..................................................................................................................... 20
• Added content to the HCSL section .................................................................................................................................... 21
• Changed the VCXO Buffered Output section ...................................................................................................................... 22
3
LMK04610
www.ti.com.cn
ZHCSG17B –JANUARY 2017–REVISED JULY 2019
版权 © 2017–2019, Texas Instruments Incorporated
修修订订历历史史记记录录 (接接下下页页)
• Changed VCO frequency to 5870 MHz to 6175 MHz and updated max output frequency to 2058 MHz ........................... 23
• Added content to the Programmable Output Formats section ............................................................................................ 23
• Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 31
• Changed HCSL to LVPECL graphic..................................................................................................................................... 31
• Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 32
• Changed HSDS to LVPECL graphic .................................................................................................................................... 32
• Added content to the OSCout section ................................................................................................................................. 35
• Added OSCin to OSCout differential results in clock inversion from OSCin to OSCout. .................................................... 35
• Added Note to use TICS Pro EVM tool to calculate SDPLL loop filter values. .................................................................... 38
• Changed PLL1_PROP max from 255 to 127. ..................................................................................................................... 38
• Added PLL1_PROP_FL to table. ......................................................................................................................................... 38
• Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for Low Pulse mode......................................................................... 38
• Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for High Pulse mode ....................................................................... 38
• Deleted Examples of PLL1 Setting....................................................................................................................................... 38
• Changed the tuning range of the oscillator from: 5800 MHz to: 5870 MHz ......................................................................... 40
• Added PLL2 DLD programming information and updated the PLLx DLD flowchart graphic .............................................. 41
• Changed PLL1_STORAGE_CELL description from 40-bit thermometer code to 6-bit decimal value ................................ 44
• Clarified CTRL_VCXO represented as PLL1_STORAGE_CELL value .............................................................................. 44
• Changed section from: Low Skew Mode to: Zero Delay Mode (ZDM) ................................................................................ 49
• Changed Set Prop/Store-CP from "fast lock" value to "non-fast lock" value at end of flowchart......................................... 51
• Deleted references to tunable crystal .................................................................................................................................. 52
• Deleted reference to CLKin2 and CLKin3 ........................................................................................................................... 52
• Deleted use of external VCO for PLL2................................................................................................................................. 52
• Added register 0x85, 0x86, 0xF6, and 0xAD for PLL2 DLD to recommended programming sequence ............................. 55
• Changed PLL1_PROP from 8 bit to 7 bit field in register map ............................................................................................ 59
• Changed PLL1_PROP_FL from 8 bit to 7 bit field in register map ..................................................................................... 59
• Changed PLL1_STORAGE_CELL 40 bit to 6 bit field. Not a 40 bit thermometer code. Set registers 0x66, 0x67,
0x68, 0x69 to RSRVD in register map ................................................................................................................................ 59
• Changed PLL2_PROP from 8 bit to 6 bit field in register map ............................................................................................ 60
• Changed PLL2_INTG from 8 bit to 5 bit field in register map ............................................................................................. 60
• Added register 0xAC for field PLL1_TSTMODE_REF_FB_EN in register map................................................................... 61
• Added register 0xAD for fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO in register
map....................................................................................................................................................................................... 61
• Added register 0xF6 for PLL2_DLD_EN in register map ..................................................................................................... 61
• Deleted unused DEVID values ............................................................................................................................................. 65
• Changed reset value for CHIPID from 0x1 to 0x3................................................................................................................ 65
• Changed reset value for CHIPVER from 0x1 to 0x1B ......................................................................................................... 65
• Changed PLL1_PROP from 8 bit to 7 bit field in register definition .................................................................................... 85
• Changed PLL1_PROP_FL from 8 bit to 7 bit field in register definition .............................................................................. 85
• Deleted 'PLL1 Start-up in Holdover.' text from the PLL1_STARTUP_HOLDOVER_EN bit description .............................. 85
• Changed PLL2_PROP field size from 8 bits to 6 bits in register definition ......................................................................... 90
• Changed PLL2_INTG field from 8 bit to 5 bit field in register 0x80 definition ...................................................................... 92
• Added definition and requirement for setting PLL2_LD_WNDW_SIZE = 0 in register 0x85 definition ............................... 93
• Added definition and requirement for setting PLL2_LD_WNDW_SIZE_INITIAL = 0 in register 0x86 definition.................. 93
• Added note for using PLL1/2 REF/FB(SYS) status output for STAT0 ................................................................................ 96
• Added note for using PLL1/2 REF/FB(SYS) status output for STAT1 ................................................................................ 97
4
LMK04610
ZHCSG17B –JANUARY 2017–REVISED JULY 2019
www.ti.com.cn
Copyright © 2017–2019, Texas Instruments Incorporated
修修订订历历史史记记录录 (接接下下页页)
• Added note for using PLL1/2 REF/FB(SYS) status output for SYNC ............................................................................... 100
• Added register 0xAC to register description. New field PLL1_TSTMODE_REF_FB_EN. ................................................. 101
• Added register 0xAD to register description. New fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and
PD_VCO_LDO.................................................................................................................................................................... 101
• Added register 0xF6 to register description. New field PLL2_DLD_EN ............................................................................. 102
• Added register 0xF7 to register description. New field PLL2_DUAL_LOOP_EN .............................................................. 102
• Changed Channel 5 and 6 FBClock Buffers from: Low Skew to: Zero Delay Mode.......................................................... 112
• Changed registers for WINDOW SIZE and LOCK COUNT. Updated equation to reflect the more general WINDOW
SIZE and LOCK COUNT names and count frequency. Removed reference to holdover. Updated descriptive text ........ 116
• Updated minimum lock time calculation example to reflect updated register names and count frequency ...................... 116
• Simplified HSDS format description .................................................................................................................................. 121
Changes from Original (January 2017) to Revision A Page
• 从 LMK04610 中删除了 16 个差动 输出 时钟和 6 个频率组特性 ........................................................................................... 1
• 删除了 LMK04610 中的 4 个基准输入特性 ............................................................................................................................. 1
• 将文本从“–70dBc PSRR”更改为“–80dBc PSRR（在 VDDO 上）.......................................................................................... 1
• 将 SPI 接口默认设置从 3 线制更改为 4 线制.......................................................................................................................... 1
• 将 VCO 频率从“5.8GHz 至 6.2GHz”更改为“5.8GHz 至 6.175GHz”........................................................................................ 1
• Changed VCO frequency from: 6200 MHz to: 6175 MHz ...................................................................................................... 4
• Updated PLL1_CAP pin description ....................................................................................................................................... 6
• Removed tablenote from the doubler input frequency parameter........................................................................................ 11
• Changed VCO tuning range maximum from: 6200 to: 6175 ................................................................................................ 11
• Changed tablenote text from: ATE tested at 2949.12 MHz to: ATE tested at 258 MHz...................................................... 11
• Removed the CLKin2/CLKin2*, and CLKin3/CLKin3* inputs from the LMK04610............................................................... 22
• Updated the Functional Block Diagram................................................................................................................................ 24
• Added content to the Driving CLKin and OSCin Pins With a Differential Source section.................................................... 28
• Changed text from: Either AC coupling or DC coupling may be used. to: The clock is internally AC-coupled.................... 29
• Updated Figure 36 ............................................................................................................................................................... 37
• Changed the tuning range of the oscillator from: 6200 MHz to: 6175 MHz ......................................................................... 40
• Updated Figure 49 ............................................................................................................................................................... 50
• Changed the caption title on Figure 53 ............................................................................................................................... 52
• Changed the caption title on Figure 54 ............................................................................................................................... 53
• Changed the caption title on Figure 55 ................................................................................................................................ 53
(1) Refer to LMK04616 datasheet.
5 Device Comparison Table
Table 1. Device Configuration Information
PART NUMBER
REFEREN
CE
INPUTS
OSCout (BUFFERED
OSCin OR PLL2 CLOCK)
HCSL/ HSDS/ LVCMOS
PLL2
PROGRAMMABLE
HCSL/HSDS
OUTPUTS
VCO FREQUENCY PACKAGE
LMK04610 2 1 10 5870 to 6175 MHz VQFN-56
LMK04616 4 1 16 5870 to 6175 MHz NFBGA-144
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
42
41
40
39
38
37
36
35
34
33
32
31
30
29
43
44
45
46
47
48
49
50
51
52
53
54
55
56
56 pin QFN
Top down view
DAP = GND
OSCin*
OSCin
OSCout*
OSCout
VDD_OSC
NC
PLL2_VCO_LDO_CAP
PLL2_LDO_CAP
VDD_PLL2OSC
VDD_PLL2CORE
CLKout4
CLKout4*
CLKout8
CLKout8*
CLKout6
CLKout6*
CLKout7
CLKout7*
CTRL_VCXO
VDDO_9/10
VDD_PLL1
VDDO_6
CLKout9*
CLKout9
SCL
SDIO
CLKin_SEL
CLKin0*
CLKin0
CLKin1
CLKin1*
SYNC
SCS*
CLKout10
CLKout10*
VDD_CORE
VDD_IO
CLKout2
CLKout3
CLKout3*
CLKout2*
VDDO_5
VDDO_3/4
CLKout1
CLKout1*
NC
VDDO_7/8
CLKout5
CLKout5*
RESETN
VDDO_1/2
NC
NC
PLL1_CAP
STATUS1
STATUS0
5
LMK04610
www.ti.com.cn
ZHCSG17B –JANUARY 2017–REVISED JULY 2019
Copyright © 2017–2019, Texas Instruments Incorporated
6 Pin Configuration and Functions
RTQ Package
56-Pin VQFN
Top View
A. LMK04610
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