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TI-LMK02000.pdf
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK02000
SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007
Precision Clock Conditioner with Integrated PLL
Check for Samples: LMK02000
All trademarks are the property of their respective owners.
1
1 Features
1
• 20 fs Additive Jitter
• Integrated Integer-N PLL with Outstanding
Normalized Phase Noise Contribution of -224
dBc/Hz
• Clock Output Frequency Range of 1 to 800 MHz
• 3 LVDS and 5 LVPECL Clock Outputs
• Dedicated Divider and Delay Blocks on Each
Clock Output
• Pin Compatible Family of Clocking Devices
• 3.15 to 3.45 V Operation
• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
2 Target Applications
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Wireless Infrastructure
• Medical
• Test and Measurement
• Military / Aerospace
3 Description
The LMK02000 precision clock conditioner combines
the functions of jitter cleaning/reconditioning,
multiplication, and distribution of a reference clock.
The device integrates a high performance Integer-N
Phase Locked Loop (PLL), three LVDS, and five
LVPECL clock output distribution blocks.
Each clock distribution block includes a
programmable divider, a phase synchronization
circuit, a programmable delay, a clock output mux,
and an LVDS or LVPECL output buffer. This allows
multiple integer-related and phase-adjusted copies of
the reference to be distributed to eight system
components.
The clock conditioner comes in a 48-pin WQFN
package and is footprint compatible with other
clocking devices in the same family.
OSCin
OSCin*
R Divider
Phase
Detector
N Divider
CLKout0
CLKout0*
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
CLKout4
CLKout4*
CLKout5
CLKout5*
CLKout6
CLKout6*
CLKout7
CLKout7*
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Distribution Path
CLK
DATA
LE
Control
Registers
PWire
Port
Device
Control
LDGOE
SYNC*
Fin
Fin*
Charge
Pump
CPout
Low Clock Buffers
High Clock Buffers
2
LMK02000
SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007
www.ti.com
Product Folder Links: LMK02000
Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated
3.1 Functional Block Diagram
GND
NC
Vcc1
Vcc2
Vcc3
Vcc4
Vcc5
Vcc6
Vcc7
Vcc8
Vcc9
Vcc10
Vcc11
Vcc12
Vcc13
Vcc14
CLKuWire
DATAuWire
LEuWire
NC
LDObyp1
LDObyp2
GOE
LD
CLKout0
CLKout0*
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
GND
SYNC*
OSCin
OSCin*
CPout
Fin
Fin*
Bias
CLKout4
CLKout4*
CLKout5
CLKout5*
CLKout6
CLKout6*
CLKout7
CLKout7*
WQFN-48
Top Down View
4748 46 45 44 43 42 41 40 39 38 37
11
12
10
9
8
7
6
5
4
3
2
1
1413 15 16 17 18 19 20 21 22 23 24
26
25
27
28
29
30
31
32
33
34
35
36
DAP
3
LMK02000
www.ti.com
SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007
Product Folder Links: LMK02000
Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated
3.2 Connection Diagram
Figure 1. 48-Pin WQFN Package
Pin Descriptions
Pin # Pin Name I/O Description
1, 25 GND - Ground
2, 7 NC - No Connection to these pins
3, 8, 13, 16, 19, 22, 26,
30, 31, 33, 37, 40, 43, 46
Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8,
Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14
- Power Supply
4 CLKuWire I MICROWIRE Clock Input
5 DATAuWire I MICROWIRE Data Input
6 LEuWire I MICROWIRE Latch Enable Input
9, 10 LDObyp1, LDObyp2 - LDO Bypass
11 GOE I Global Output Enable
12 LD O Lock Detect and Test Output
14, 15 CLKout0, CLKout0* O LVDS Clock Output 0
17, 18 CLKout1, CLKout1* O LVDS Clock Output 1
20, 21 CLKout2, CLKout2* O LVDS Clock Output 2
23, 24 CLKout3, CLKout3* O LVPECL Clock Output 3
27 SYNC* I Global Clock Output Synchronization
28, 29 OSCin, OSCin* I Oscillator Clock Input; Must be AC coupled
4
LMK02000
SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007
www.ti.com
Product Folder Links: LMK02000
Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated
Connection Diagram (continued)
Pin Descriptions (continued)
Pin # Pin Name I/O Description
32 CPout O Charge Pump Output
34, 35 Fin, Fin* I Frequency Input; Must be AC coupled
36 Bias I Bias Bypass
38, 39 CLKout4, CLKout4* O LVPECL Clock Output 4
41, 42 CLKout5, CLKout5* O LVPECL Clock Output 5
44, 45 CLKout6, CLKout6* O LVPECL Clock Output 6
47, 48 CLKout7, CLKout7* O LVPECL Clock Output 7
DAP DAP - Die Attach Pad is Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD
protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
4 Absolute Maximum Ratings
(1)(2)(3)
Parameter Symbol Ratings Units
Power Supply Voltage V
CC
-0.3 to 3.6 V
Input Voltage V
IN
-0.3 to (V
CC
+ 0.3) V
Storage Temperature Range T
STG
-65 to 150 °C
Lead Temperature (solder 4 s) T
L
+260 °C
Junction Temperature T
J
125 °C
5 Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Ambient Temperature T
A
-40 25 85 °C
Power Supply Voltage V
CC
3.15 3.3 3.45 V
(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These
vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in
the board layout.
6 Package Thermal Resistance
Package θ
JA
θ
J-PAD (Thermal Pad)
48-Lead WQFN
(1)
27.4° C/W 5.8° C/W
5
LMK02000
www.ti.com
SNAS390D –NOVEMBER 2006–REVISED SEPTEMBER 2007
Product Folder Links: LMK02000
Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) See CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS for more current consumption / power dissipation
calculation information.
(3) For all frequencies the slew rate, SLEW
Fin
, is measured between 20% and 80%.
(4) Specification is ensured by characterization and is not tested in production.
(5) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
PLL_flicker
(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
PLL_flicker
(10
kHz) - 20log(Fout / 1 GHz), where L
PLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure L
PLL_flicker
(f) it is important to be on the 10 dB/decade slope close to the carrier. A high phase detector frequency and a
clean crystal are important to isolating this noise source from the total phase noise, L(f). L
PLL_flicker
(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of L
PLL_flicker
(f)
and L
PLL_flat
(f).
7 Electrical Characteristics
(1)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T
A
≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most
likely parametric norms at Vcc = 3.3 V, T
A
= 25 °C, and at the Recommended Operation Conditions at the time of product
characterization and are not specified).
Symbol Parameter Conditions Min Typ Max Units
Current Consumption
I
CC
Power Supply Current
(2)
Entire device; CLKout0 & CLKout4
enabled in Bypass Mode
145.8
mA
Entire device; All Outputs Off (no
emitter resistors placed)
70
I
CC
PD Power Down Current POWERDOWN = 1 1 mA
Reference Oscillator
f
OSCin
square
Reference Oscillator Input Frequency
Range for Square Wave
AC coupled; Differential (V
OD
)
1 200 MHz
V
OSCin
square
Square Wave Input Voltage for OSCin and
OSCin*
0.2 1.6 Vpp
Frequency Input
f
Fin
Frequency Input Frequency Range 1 800 MHz
SLEW
Fin
Frequency Input Slew Rate
(3)(4)
0.5 V/ns
DUTY
Fin
Frequency Input Duty Cycle 40 60 %
P
Fin
Input Power Range for Fin or Fin* AC coupled -13 8 dBm
PLL
f
COMP
Phase Detector Frequency 40 MHz
I
SRCE
CPout Charge Pump Source Current
V
CPout
= Vcc/2, PLL_CP_GAIN = 1x 100
µA
V
CPout
= Vcc/2, PLL_CP_GAIN = 4x 400
V
CPout
= Vcc/2, PLL_CP_GAIN = 16x 1600
V
CPout
= Vcc/2, PLL_CP_GAIN = 32x 3200
I
SINK
CPout Charge Pump Sink Current
V
CPout
= Vcc/2, PLL_CP_GAIN = 1x -100
μA
V
CPout
= Vcc/2, PLL_CP_GAIN = 4x -400
V
CPout
= Vcc/2, PLL_CP_GAIN = 16x -1600
V
CPout
= Vcc/2, PLL_CP_GAIN = 32x -3200
I
CPout
TRI Charge Pump TRI-STATE Current 0.5 V < V
CPout
< Vcc - 0.5 V 2 10 nA
I
CPout
%MIS
Magnitude of Charge Pump
Sink vs. Source Current Mismatch
V
CPout
= Vcc / 2
T
A
= 25°C
3 %
I
CPout
VTUNE
Magnitude of Charge Pump
Current vs. Charge Pump Voltage Variation
0.5 V < V
CPout
< Vcc - 0.5 V
T
A
= 25°C
4 %
I
CPout
TEMP
Magnitude of Charge Pump Current vs.
Temperature Variation
4 %
PN10kHz
PLL 1/f Noise at 10 kHz Offset
(5)
Normalized to 1 GHz Output Frequency
PLL_CP_GAIN = 1x -117
dBc/Hz
PLL_CP_GAIN = 32x -122
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