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TI-LMK02002.pdf
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OSCin
OSCin*
R Divider
Phase
Detector
N Divider
CLKout0
CLKout0*
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Divider
Delay
Mux
Distribution Path
CLK
DATA
LE
Control
Registers
PWire
Port
Device
Control
LDGOE
SYNC*
CPout
Clock Buffers
Fin
Fin*
Charge
Pump
LMK02002
www.ti.com
SNAS418 –AUGUST 2007
LMK02002 Precision Clock Conditioner with Integrated PLL
Check for Samples: LMK02002
1
FEATURES
DESCRIPTION
The LMK02002 precision clock conditioner combines
2
• 20 fs Additive Jitter
the functions of jitter cleaning/reconditioning,
• Integrated Integer-N PLL with Outstanding
multiplication, and distribution of a reference clock.
Normalized Phase Noise Contribution of -224
The device integrates a high performance Integer-N
dBc/Hz
Phase Locked Loop (PLL), and four LVPECL clock
output distribution blocks.
• Clock Output Frequency Range of 1 to 800
MHz
Each clock distribution block includes a
• 4 LVPECL Clock Outputs
programmable divider, a phase synchronization
circuit, a programmable delay, a clock output mux,
• Dedicated Divider and Delay Blocks on Each
and an LVPECL output buffer. This allows multiple
Clock Output
integer-related and phase-adjusted copies of the
• Pin Compatible Family of Clocking Devices
reference to be distributed to eight system
• 3.15 to 3.45 V Operation
components.
• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
The clock conditioner comes in a 48-pin WQFN
package and is footprint compatible with other
TARGET APPLICATIONS
clocking devices in the same family.
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Wireless Infrastructure
• Medical
• Test and Measurement
• Military / Aerospace
Functional Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
4748 46 45 44 43 42 41 40 39 38 37
11
12
10
9
8
7
6
5
4
3
2
1
1413 15 16 17 18 19 20 21 22 23 24
26
25
27
28
29
30
31
32
33
34
35
36GND
NC
Vcc1
Vcc2
Vcc3
Vcc4
Vcc5
Vcc6
Vcc7
Vcc8
Vcc9
Vcc10
Vcc11
Vcc12
Vcc13
Vcc14
CLKuWire
DATAuWire
LEuWire
NC
LDObyp1
LDObyp2
GOE
LD
NC
NC
NC
NC
NC
NC
NC
NC
GND
SYNC*
OSCin
OSCin*
CPout
Fin
Fin*
Bias
CLKout0
CLKout0*
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
DAP
WQFN-48
Top Down View
LMK02002
SNAS418 –AUGUST 2007
www.ti.com
Connection Diagram
Figure 1. 48-Pin WQFN Package
Pin Descriptions
Pin # Pin Name I/O Description
1, 25 GND - Ground
2, 7, 14, 15, 17, 18, 20,
NC - No Connection to these pins
21, 23, 24
3, 8, 13, 16, 19, 22, 26, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8,
- Power Supply
30, 31, 33, 37, 40, 43, 46 Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14
4 CLKuWire I MICROWIRE Clock Input
5 DATAuWire I MICROWIRE Data Input
6 LEuWire I MICROWIRE Latch Enable Input
9, 10 LDObyp1, LDObyp2 - LDO Bypass
11 GOE I Global Output Enable
12 LD O Lock Detect and Test Output
27 SYNC* I Global Clock Output Synchronization
28, 29 OSCin, OSCin* I Oscillator Clock Input; Must be AC coupled
32 CPout O Charge Pump Output
34, 35 Fin, Fin* I Frequency Input; Must be AC coupled
36 Bias I Bias Bypass
38, 39 CLKout0, CLKout0* O LVPECL Clock Output 0
41, 42 CLKout1, CLKout1* O LVPECL Clock Output 1
2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Links: LMK02002
LMK02002
www.ti.com
SNAS418 –AUGUST 2007
Pin Descriptions (continued)
Pin # Pin Name I/O Description
44, 45 CLKout2, CLKout2* O LVPECL Clock Output 2
47, 48 CLKout3, CLKout3* O LVPECL Clock Output 3
DAP DAP - Die Attach Pad is Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)(3)
Parameter Symbol Ratings Units
Power Supply Voltage V
CC
-0.3 to 3.6 V
Input Voltage V
IN
-0.3 to (V
CC
+ 0.3) V
Storage Temperature Range T
STG
-65 to 150 °C
Lead Temperature (solder 4 s) T
L
+260 °C
Junction Temperature T
J
125 °C
(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD
protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Ambient Temperature T
A
-40 25 85 °C
Power Supply Voltage V
CC
3.15 3.3 3.45 V
Package Thermal Resistance
Package θ
JA
θ
J-PAD (Thermal Pad)
48-Lead WQFN
(1)
27.4° C/W 5.8° C/W
(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These
vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in
the board layout.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMK02002
LMK02002
SNAS418 –AUGUST 2007
www.ti.com
Electrical Characteristics
(1)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T
A
≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most
likely parametric norms at Vcc = 3.3 V, T
A
= 25 °C, and at the Recommended Operation Conditions at the time of product
characterization and are not specified).
Symbol Parameter Conditions Min Typ Max Units
Current Consumption
Entire device; CLKout0 & CLKout3
159
enabled in Bypass Mode
I
CC
Power Supply Current
(2)
mA
Entire device; All Outputs Off (no
70
emitter resistors placed)
I
CC
PD Power Down Current POWERDOWN = 1 1 mA
Reference Oscillator
Reference Oscillator Input Frequency
f
OSCin
square 1 200 MHz
Range for Square Wave
AC coupled; Differential (V
OD
)
Square Wave Input Voltage for OSCin and
V
OSCin
square 0.2 1.6 Vpp
OSCin*
Frequency Input
f
Fin
Frequency Input Frequency Range 1 800 MHz
SLEW
Fin
Frequency Input Slew Rate See
(3)(4)
0.5 V/ns
DUTY
Fin
Frequency Input Duty Cycle 40 60 %
P
Fin
Input Power Range for Fin or Fin* AC coupled -13 8 dBm
PLL
f
COMP
Phase Detector Frequency 40 MHz
V
CPout
= Vcc/2, PLL_CP_GAIN = 1x 100
V
CPout
= Vcc/2, PLL_CP_GAIN = 4x 400
I
SRCE
CPout Charge Pump Source Current µA
V
CPout
= Vcc/2, PLL_CP_GAIN = 16x 1600
V
CPout
= Vcc/2, PLL_CP_GAIN = 32x 3200
V
CPout
= Vcc/2, PLL_CP_GAIN = 1x -100
V
CPout
= Vcc/2, PLL_CP_GAIN = 4x -400
I
SINK
CPout Charge Pump Sink Current μA
V
CPout
= Vcc/2, PLL_CP_GAIN = 16x -1600
V
CPout
= Vcc/2, PLL_CP_GAIN = 32x -3200
I
CPout
TRI Charge Pump TRI-STATE Current 0.5 V < V
CPout
< Vcc - 0.5 V 2 10 nA
Magnitude of Charge Pump V
CPout
= Vcc / 2
I
CPout
%MIS 3 %
Sink vs. Source Current Mismatch T
A
= 25°C
Magnitude of Charge Pump 0.5 V < V
CPout
< Vcc - 0.5 V
I
CPout
VTUNE 4 %
Current vs. Charge Pump Voltage Variation T
A
= 25°C
Magnitude of Charge Pump Current vs.
I
CPout
TEMP 4 %
Temperature Variation
PLL_CP_GAIN = 1x -117
PLL 1/f Noise at 10 kHz Offset
(5)
PN10kHz dBc/Hz
Normalized to 1 GHz Output Frequency
PLL_CP_GAIN = 32x -122
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) See CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS for more current consumption / power dissipation
calculation information.
(3) For all frequencies the slew rate, SLEW
Fin
, is measured between 20% and 80%.
(4) Specification is ensured by characterization and is not tested in production.
(5) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
PLL_flicker
(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
PLL_flicker
(10
kHz) - 20log(Fout / 1 GHz), where L
PLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure L
PLL_flicker
(f) it is important to be on the 10 dB/decade slope close to the carrier. A high phase detector frequency and a
clean crystal are important to isolating this noise source from the total phase noise, L(f). L
PLL_flicker
(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of L
PLL_flicker
(f)
and L
PLL_flat
(f).
4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Links: LMK02002
LMK02002
www.ti.com
SNAS418 –AUGUST 2007
Electrical Characteristics
(1)
(continued)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T
A
≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most
likely parametric norms at Vcc = 3.3 V, T
A
= 25 °C, and at the Recommended Operation Conditions at the time of product
characterization and are not specified).
Symbol Parameter Conditions Min Typ Max Units
PLL_CP_GAIN = 1x -219
PN1Hz Normalized Phase Noise Contribution
(6)
dBc/Hz
PLL_CP_GAIN = 32x -224
Clock Distribution Section
(7)
- LVPECL Clock Outputs (CLKout0 to CLKout3)
CLKoutX_MUX =
20
R
L
= 100 Ω
Bypass
Distribution Path =
CLKoutX_MUX =
Jitter
ADD
Additive RMS Jitter
(7)
800 MHz fs
Divided
Bandwidth =
75
CLKoutX_DIV =
12 kHz to 20 MHz
4
Equal loading and identical clock
t
SKEW
CLKoutX to CLKoutY
(4)
configuration -30 ±3 30 ps
Termination = 50 Ω to Vcc - 2 V
Vcc -
V
OH
Output High Voltage V
0.98
Termination = 50 Ω to Vcc - 2 V
Vcc -
V
OL
Output Low Voltage CLKoutX output frequency = 200 MHz V
1.8
V
OD
Differential Output Voltage 660 810 965 mV
Digital LVTTL Interfaces
(8)
V
IH
High-Level Input Voltage 2.0 Vcc V
V
IL
Low-Level Input Voltage 0.8 V
I
IH
High-Level Input Current V
IH
= Vcc -5.0 5.0 µA
I
IL
Low-Level Input Current V
IL
= 0 -40.0 5.0 µA
Vcc -
V
OH
High-Level Output Voltage I
OH
= +500 µA V
0.4
V
OL
Low-Level Output Voltage I
OL
= -500 µA 0.4 V
Digital MICROWIRE Interfaces
(9)
V
IH
High-Level Input Voltage 1.6 Vcc V
V
IL
Low-Level Input Voltage 0.4 V
I
IH
High-Level Input Current V
IH
= Vcc -5.0 5.0 µA
I
IL
Low-Level Input Current V
IL
= 0 -5.0 5.0 µA
MICROWIRE Timing
t
CS
Data to Clock Set Up Time See Data Input Timing 25 ns
t
CH
Data to Clock Hold Time See Data Input Timing 8 ns
t
CWH
Clock Pulse Width High See Data Input Timing 25 ns
t
CWL
Clock Pulse Width Low See Data Input Timing 25 ns
t
ES
Clock to Enable Set Up Time See Data Input Timing 25 ns
t
CES
Enable to Clock Set Up Time See Data Input Timing 25 ns
t
EWH
Enable Pulse Width High See Data Input Timing 25 ns
(6) A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L
PLL_flat
(f), of the PLL and is defined
as PN1Hz = L
PLL_flat
(f) – 20log(N) – 10log(f
COMP
). L
PLL_flat
(f) is the single side band phase noise measured at an offset frequency, f, in a
1 Hz Bandwidth and f
COMP
is the phase detector frequency of the synthesizer. L
PLL_flat
(f) contributes to the total noise, L(f). To measure
L
PLL_flat
(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid
a substantial noise contribution from the reference and flicker noise. L
PLL_flat
(f) can be masked by the reference oscillator performance if
a low power or noisy source is used.
(7) The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the
clock distribution section only.
(8) Applies to GOE, LD, and SYNC*.
(9) Applies to CLKuWire, DATAuWire, and LEuWire.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMK02002
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