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LMK04228
ZHCSK16A –OCTOBER 2017–REVISED JULY 2019
www.ti.com.cn
版权 © 2017–2019, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions......................... 4
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 SPI Interface Timing ............................................... 13
7.7 Timing Diagram....................................................... 13
8 Parameter Measurement Information ................ 15
8.1 Charge Pump Current Specification Definitions...... 15
8.2 Differential Voltage Measurement Terminology ..... 16
9 Detailed Description............................................ 17
9.1 Overview ................................................................. 17
9.2 Functional Block Diagrams ..................................... 20
9.3 Feature Description................................................. 23
9.4 Programming........................................................... 32
9.5 Register Maps ........................................................ 33
10 Application and Implementation........................ 75
10.1 Application Information.......................................... 75
10.2 Typical Application ................................................ 78
10.3 Do's and Don'ts..................................................... 79
11 Power Supply Recommendations ..................... 80
11.1 Current Consumption / Power Dissipation
Calculations.............................................................. 80
12 Layout................................................................... 81
12.1 Layout Guidelines ................................................. 81
12.2 Layout Example .................................................... 82
13 器器件件和和文文档档支支持持 ..................................................... 83
13.1 器件支持................................................................ 83
13.2 社区资源................................................................ 83
13.3 商标 ....................................................................... 83
13.4 静电放电警告......................................................... 83
13.5 Glossary................................................................ 83
14 机机械械、、封封装装和和可可订订购购信信息息....................................... 83
4 修修订订历历史史记记录录
Changes from Original (October 2017) to Revision A Page
• 将数据表版本状态从产品定制更改为产品目录........................................................................................................................ 1
• 已删除 删除了有关分配模式的参考内容（不支持）................................................................................................................ 1
• 已删除 删除了有关动态延迟的参考内容（不支持）................................................................................................................ 1
• Updated default output table note ........................................................................................................................................ 11
• Added missing cross reference to differential voltage definition .......................................................................................... 12
• Removed typical phase noise plots ..................................................................................................................................... 13
• Updated description for improved clarity .............................................................................................................................. 17
• Deleted reference to distribution mode (unsupported) ......................................................................................................... 17
• Updated delay circuit descriptions for improved clarity ........................................................................................................ 18
• Deleted reference to dynamic delay (unsupported) ............................................................................................................. 19
• Deleted reference to dynamic delay, bypass mode in clock output block diagram (unsupported) ...................................... 21
• Deleted reference to distribution mode in SYNC/SYSREF clocking path diagram (unsupported) ...................................... 22
• Clarified digital lock detect for cases where phase detector frequency exceeds default PLL1_WND_SIZE ...................... 29
• Removed device functional modes section .......................................................................................................................... 32
• Clarified requirements for unused registers in recommended programming sequence....................................................... 32
• Added registers 0x171 and 0x172 to default register programming .................................................................................... 32
• Deleted redundant user-inaccessible registers in register map ........................................................................................... 33
• Changed address bits to clarify address position relative to data bits ................................................................................. 33
• Deleted references to dynamic delay in register map (unsupported)................................................................................... 33
• Corrected CLKinX_R register size in register map............................................................................................................... 35
• Corrected PLL1_N register size in register map .................................................................................................................. 35
• Deleted reference to DCLKoutX_MUX bypass mode (unsupported)................................................................................... 40
• Corrected delay value descriptions for SDCLKoutY_ADLY ................................................................................................. 41
• Deleted reference to dynamic delay (unsupported) ............................................................................................................. 42
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