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TI-LMK04133.pdf
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TI-LMK04133.pdf
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CLK
DATA
LE
PWire
Port
SYNC*
Internal
VCO
CLKin1
PLL1
GOE
PLL2
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
External VCXO or
low cost crystal
CLKin0
OSCin (Single ended or differential)
LMK04100, LMK04101, LMK04102, LMK04110
LMK04111, LMK04131, LMK04133
www.ti.com
SNAS516B –APRIL 2011–REVISED NOVEMBER 2012
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs
Check for Samples: LMK04100, LMK04101, LMK04102, LMK04110, LMK04111, LMK04131, LMK04133
1
FEATURES
23
• Cascaded PLLatinum™ PLL Architecture
• Industrial Temperature Range: -40 to 85 °C
– PLL1 • 3.15 V to 3.45 V Operation
– Redundant Reference Inputs • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
– Loss of Signal Detection
APPLICATIONS
– Automatic and Manual Selection of
• Multi-Carrier/Multi-Mode/Multi-Band 2G/3G/4G
Reference Clock Input
Basestations
– PLL2
• Cellular Repeaters
– Phase Detector Rate up to 100 MHz
• High Speed A/D clocking
– Input Frequency-Doubler
• SONET/SDH OC-48/OC-192/OC-768 Line Cards
– Integrated VCO
• GbE/10GbE, 1/2/4/8/10G Fibre Channel Line
• Outputs
Cards
– LVPECL/2VPECL, LVDS, and LVCMOS
• Optical Transport Networks
Formats
• Broadcast Video, HDTV
– Support Clock Rates up to 1080 MHz
• Serial ATA
– Five Dedicated Channel Divider Blocks
– Common Output Frequencies Supported:
DESCRIPTION
– 30.72 MHz, 61.44 MHz, 62.5 MHz, 74.25
The LMK04100 family of precision clock conditioners
MHz, 75 MHz, 77.76 MHz, 100 MHz,
provides jitter cleaning, clock multiplication and
106.25 MHz, 125 MHz, 122.88 MHz, 150
distribution without the need for high-performance
MHz, 155.52 MHz, 156.25 MHz, 159.375
VCXO modules.
MHz, 187.5 MHz, 200 MHz, 212.5 MHz,
When connected to a recovered system reference
245.76 MHz, 250 MHz, 311.04 MHz, 312.5
clock and a VCXO, the device generates 5 low jitter
MHz, 368.64 MHz, 491.52 MHz, 622.08
clocks in LVCMOS, LVDS, or LVPECL formats.
MHz, 625 MHz, 983.04 MHz
• MICROWIRE (SPI) Programming Interface
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PLLatinum is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMK04100, LMK04101, LMK04102, LMK04110
LMK04111, LMK04131, LMK04133
SNAS516B –APRIL 2011–REVISED NOVEMBER 2012
www.ti.com
Table 1. Device Configuration Information
2VPECL / LVPECL
NSID LVDS OUTPUTS LVCMOS OUTPUTS VCO
OUTPUTS
LMK04100SQ 3 4 1185 to 1296 MHz
LMK04101SQ 3 4 1430 to 1570 MHz
LMK04102SQ 3 4 1600 to 1750 MHz
LMK04110SQ 5 1185 to 1296 MHz
LMK04111SQ 5 1430 to 1570 MHz
LMK04131SQ 2 2 2 1430 to 1570 MHz
LMK04133SQ 2 2 2 1840 to 2160 MHz
Table 2. Device Output Format Information
NSID CLKout0 CLKout1 CLKout2 CLKout3 CLKout4
LMK04100SQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04101SQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04102SQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04110SQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL
LMK04111SQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL
LMK04131SQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS
LMK04133SQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS
Table 3 shows a limited list of example frequencies. Multiple output frequencies can be programmed on a single
device provided that the VCO frequency and VCO divider values are the same.
2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: LMK04100 LMK04101 LMK04102 LMK04110 LMK04111 LMK04131 LMK04133
LMK04100, LMK04101, LMK04102, LMK04110
LMK04111, LMK04131, LMK04133
www.ti.com
SNAS516B –APRIL 2011–REVISED NOVEMBER 2012
Table 3. Example Configurations for Common Frequencies
VCO Frequency Output
OSCin (MHz) VCO Divider PLL2 N Output Divider Application
(1)
Frequency
25 2 30 1500 12 62.5 GigE
25 2 30 1500 10 75 SATA
24.8832 2 25 1244.16 8 77.76 SONET
25 2 24 1200 6 100 PCI Express
26.5625 7 8 1487.5 2 106.25 Fibre Channel
25 2 30 1500 6 125 GigE
25 5 12 1500 2 150 SATA
24.8832 2 25 1244.16 4 155.52 SONET
25 2 25 1250 4 156.25 10 GigE
26.5625 2 25 1275 4 159.375 10-G Fibre
Channel
25 2 25 1500 4 187.5 12 GigE
25 3 16 1200 2 200 PCI Express
26.5625 3 16 1275 2 212.5 4-G Fibre
Channel
25 3 20 1500 2 250 GigE
24.8832 2 25 1244.16 2 311.04 SONET
25 2 25 1250 2 312.5 XGMII
24.8832 2 25 1244.16 1 622.08 SONET
25 2 25 1200 1 625 10 GigE
(1) Use VCO Frequency to select proper device option
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMK04100 LMK04101 LMK04102 LMK04110 LMK04111 LMK04131 LMK04133
OSCin
OSCin*
R1 Divider
Phase
Detector
PLL1
N1 Divider
VCO
Divider
CLKout4
CLKout4*
CLKout3B
CLKout3A
CLKout2B
CLKout2A
CLKout1
CLKout1*
CPout1
Internal VCO
Partially
Integrated
Loop Filter
Mux
Mux
Divider
Mux
Divider
Mux
Distribution
Path
CLK
DATA
LE
Control
Registers
PWire
Port
Device
Control
LD
GOE
SYNC*
Fout
Clock Buffers
Mux
Divider
Divider
CLKin0
CLKin0*
CLKin1
CLKin1*
R2 Divider
Phase
Detector
PLL2
N2 Divider
CPout2
2X
CLKout0
CLKout0*
Mux
Divider
LOS
LOS
LOS0
LOS1
Mux
LMK04100, LMK04101, LMK04102, LMK04110
LMK04111, LMK04131, LMK04133
SNAS516B –APRIL 2011–REVISED NOVEMBER 2012
www.ti.com
Functional Block Diagram
4 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: LMK04100 LMK04101 LMK04102 LMK04110 LMK04111 LMK04131 LMK04133
4748 46 45 44 43 42 41 40 39 38 37
11
12
10
9
8
7
6
5
4
3
2
1
1413 15 16 17 18 19 20 21 22 23 24
26
25
27
28
29
30
31
32
33
34
35
36GND
Fout
Vcc1
Vcc2
Vcc3
DLD_BYP
Vcc5
Vcc6
CLKin1*
Vcc8
Vcc9
Vcc10
Vcc11
Vcc12
Vcc13
Vcc14
CLKuWire
DATAuWire
LEuWire
NC
LDObyp1
LDObyp2
GOE
LD
CLKout0
CLKout0*
GND
Vcc4
CLKin0
CLKin0*
CPout1
Vcc7
CLKin1
SYNC*
OSCin
OSCin*
CPout2
CLKin0_LOS
CLKin1_LOS
Bias
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
CLKout4
CLKout4*
DAP
LMK04100, LMK04101, LMK04102, LMK04110
LMK04111, LMK04131, LMK04133
www.ti.com
SNAS516B –APRIL 2011–REVISED NOVEMBER 2012
Connection Diagram
Figure 1. 48-Pin WQFN Package
Top Down View
PIN DESCRIPTIONS
Pin Number Name(s) I/O Type Description
1 GND GND Ground (For Fout Buffer)
2 Fout O ANLG VCO Frequency Output Port
3 V
CC
1 PWR Power Supply for VCO Output Buffer
4 CLKuWire I CMOS Microwire Clock Input
5 DATAuWire I CMOS Microwire Data Input
6 LEuWire I CMOS Microwire Latch Enable Input
7 NC No Connection
8 V
CC
2 PWR Power Supply for VCO
9 LDObyp1 ANLG LDO Bypass, bypassed to ground with a 10 µF capacitor
10 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 µF
capacitor
11 GOE I CMOS Global Output Enable
12 LD O CMOS Lock Detect and PLL multiplexer Output
13 V
CC
3 PWR Power Supply for CLKout0
14 CLKout0 O LVDS/LVPECL Clock Channel 0 Output
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMK04100 LMK04101 LMK04102 LMK04110 LMK04111 LMK04131 LMK04133
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