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DAC

Recovered

³GLUW\´FORFNRU

clean clock

0XOWLSOH³FOHDQ´

clocks at different

frequencies

CLKout1 &

CLKout2

CLKout9

FPGA

CLKin0

VCXO

Backup

Reference

Clock

CLKin1

OSCout

DAC

CLKout3 &

CLKout4

ADC

LMX2582

PLL+VCO

CLKout10

CLKout7 &

CLKout8

CLKout5 &

CLKout6

LMK0461x

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS663

LMK04616

ZHCSG70B –MARCH 2017–REVISED JULY 2019

具具有有双双环环路路 PLL 且且符符合合 JESD204B 标标准准的的 LMK04616 超超低低噪噪声声和和低低功功耗耗

时时钟钟抖抖动动消消除除器器

1 特特性性

• 双环路 PLL 架构

• 超低噪声（10kHz 至 20MHz）：

– 1966.08MHz 频率下 48fs RMS 抖动

– 983.04MHz 频率下 50fs RMS 抖动

– 122.88MHz 频率下 61fs RMS 抖动

• 122.88MHz 时具有 –165dBc/Hz 本底噪声

• JESD204B 支持

– 一次性、脉冲和连续 SYSREF

• 16 个差动输出时钟（处于 8 个频率组中）

– 介于 700mVpp 和 1600mVpp 之间的可编程输

出摆幅

– 每个输出对可配置为 SYSREF 时钟输出

– 16 位通道分频器

– 最小 SYSREF 频率为 25kHz

– 最大输出频率为 2GHz

– 精密数字延迟，动态可调

– 数字延迟 (DDLY) ½ × 时钟分配路径频率

（最大 2GHz）

– 60ps 步长模拟延迟

– 50% 占空比输出分配，1 至 65535

（偶数和奇数）

• 4 个基准输入

– 输入丢失时采用保持模式

– 自动和手动切换模式

– 信号损失 (LOS) 检测

• 在 16 个有源输出下的典型功耗为 1.05W

• 通常由 1.8V（输出、输入）和 3.3V 电源（数字、

PLL1、PLL2_OSC、PLL2 内核）供电

• 完全集成的可编程环路滤波器

• PLL2

– PLL2 相位检测器频率高达 250MHz

– OSCin 倍频器

– 集成式低噪声 VCO

• 内部功率调节：优于 –80dBc PSRR（在 VDDO

上）（对于 122.88MHz 差动输出）

• 3 线制或 4 线制 SPI 接口（4 线制为默认设置）

• –40ºC 至 +85ºC 工业环境温度

• 支持 105ºC PCB 温度（在散热焊盘上测量）

• LMK04616：10mm × 10mm NFBGA-144 封装，

间距为 0.8mm

2 应应用用

• LTE-BTS、小型蜂窝、远程射频单元 (RRU) 等无

线基础设施

• 数据转换器和集成收发器时钟

• 网络、SONET/SDH、DSLAM

• 测试和测量

3 说说明明

LMK0461x 器件系列具有业界性能最高且功耗最低的

抖动清除器，支持 JESD204B 接口。可以配置 16 个

时钟输出以驱动 8 个 JESD204B 转换器或其他逻辑器

件（使用器件和 SYSREF 时钟）。可以配置第 17 个

输出，以提供来自 PLL2 的信号或来自外部 VCXO 的

副本。

完全集成的 PLL1 和 PLL2 环路滤波器、大量的集成

LDO、数字和模拟延迟、提供 3.3V、2.5V 和 1.8V 输

出的灵活性以及同时生成多个 SYSREF 域的灵活性等

特性使得该器件易于使用。

可以为传统计时系统配置 17 个输出中的每一个，不

限于 JESD204B 应用。

器器件件信信息息

(1)

器器件件型型号号 VCO 频频率率

LMK04616 5870MHz 至 6175MHz

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简简化化原原理理图图

LMK04616

ZHCSG70B –MARCH 2017–REVISED JULY 2019

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Device Comparison Table..................................... 5

6 Pin Configuration and Functions......................... 5

7 Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings.............................................................. 8

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 9

7.5 Digital Input and Output Characteristics (CLKin_SEL,

STATUSx, SYNC, RESETN) ................................... 10

7.6 Clock Input Characteristics (CLKinX)...................... 10

7.7 Clock Input Characteristics (OSCin) ....................... 11

7.8 PLL1 Specification Characteristics ......................... 12

7.9 PLL2 Specification Characteristics ......................... 12

7.10 Clock Output Type Characteristics (CLKoutX)...... 13

7.11 Oscillator Output Characteristics (OSCout) .......... 14

7.12 Jitter and Phase Noise Characteristics for CLKoutX

and OSCout ............................................................. 15

7.13 Clock Output Skew and Isolation Characteristics . 16

7.14 Clock Output Delay Characteristics ...................... 16

7.15 DEFAULT POWER on RESET CLOCK OUTPUT

Characteristics ......................................................... 16

7.16 Power Supply Characteristics ............................... 17

7.17 Typical Power Supply Noise Rejection

Characteristics ......................................................... 17

7.18 SPI Interface Timing ............................................. 18

7.19 Timing Diagram..................................................... 18

7.20 Typical Characteristics.......................................... 19

8 Parameter Measurement Information ................ 21

8.1 Differential Voltage Measurement Terminology ..... 21

8.2 Output Termination Scheme ................................... 21

9 Detailed Description............................................ 23

9.1 Overview ................................................................. 23

9.2 Functional Block Diagram ....................................... 25

9.3 Feature Description................................................. 26

9.4 Device Functional Modes........................................ 55

9.5 Programming........................................................... 57

9.6 Register Maps......................................................... 59

10 Application and Implementation...................... 122

10.1 Application Information........................................ 122

10.2 Typical Application .............................................. 123

10.3 Do's and Don'ts................................................... 125

11 Power Supply Recommendations ................... 126

11.1 Recommended Power Supply Connection ......... 126

11.2 Current Consumption / Power Dissipation

Calculations............................................................ 126

12 Layout................................................................. 127

12.1 Layout Guidelines ............................................... 127

12.2 Layout Example .................................................. 128

13 器器件件和和文文档档支支持持 ................................................... 129

13.1 器件支持 ............................................................. 129

13.2 接收文档更新通知 ............................................... 129

13.3 社区资源.............................................................. 129

13.4 商标 ..................................................................... 129

13.5 静电放电警告....................................................... 129

13.6 Glossary.............................................................. 129

14 机机械械、、封封装装和和可可订订购购信信息息..................................... 129

4 修修订订历历史史记记录录

Changes from Revision A (May 2017) to Revision B Page

• 删除了

双环路

PLL

架构

特性要点下的项目列表 ..................................................................................................................... 1

• 添加了

超低噪声

特性要点 ....................................................................................................................................................... 1

• 将 VCO 频率单位从“5.8GHz 至 6.175GHz”更改为“5870MHz 至 6175MHz” .......................................................................... 1

• Changed VCO frequency from: 5800 MHz to: 5870 MHz ...................................................................................................... 5

• Added PACKAGE column to device configuration information table ..................................................................................... 5

• Added Footnote and link to LMK04610 datasheet ................................................................................................................ 5

• Added OSCout polarity information to the OSCout/OSCout* pin description ........................................................................ 6

• Changed PLL1 phase detector maximum frequency from 40 MHz to 4 MHz ..................................................................... 12

• Changed VCO tuning range minimum from: 5800 to: 5870 ................................................................................................. 12

• Changed V

symbol to V

OD,pp

to match mVpp units. .......................................................................................................... 13

• Changed V

symbol to V

OD,pp

to match mVpp units. ......................................................................................................... 14

• Added content to the HSDS 4/6/8mA section ..................................................................................................................... 21

• Added content to the HCSL section .................................................................................................................................... 22

• Changed the VCXO Buffered Output section ...................................................................................................................... 23

• Changed VCO frequency to 5870 MHz to 6175 MHz and updated max output frequency to 2058 MHz ........................... 24

• Added content to the Programmable Output Formats section ............................................................................................ 24

LMK04616

www.ti.com.cn

ZHCSG70B –MARCH 2017–REVISED JULY 2019

修修订订历历史史记记录录 (接接下下页页)

• Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 33

• Changed HCSL to LVPECL graphic..................................................................................................................................... 33

• Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 34

• Changed HSDS to LVPECL graphic .................................................................................................................................... 34

• Added content to the OSCout section ................................................................................................................................. 37

• Added OSCin to OSCout differential results in clock inversion from OSCin to OSCout. .................................................... 37

• Added Note to use TICS Pro EVM tool to calculate SDPLL loop filter values. .................................................................... 40

• Changed PLL1_PROP max from 255 to 127. ..................................................................................................................... 40

• Added PLL1_PROP_FL to table. ......................................................................................................................................... 40

• Changed PLL1_INTG and PLL1_INTG_FL settings for specific case examples. ............................................................... 40

• Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for Low Pulse mode......................................................................... 41

• Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for High Pulse mode ....................................................................... 41

• Deleted higher order poles information ................................................................................................................................ 41

• Added C3 maximum capacitance recommendation ............................................................................................................ 41

• Deleted Examples of PLL1 Setting....................................................................................................................................... 41

• Changed the tuning range of the oscillator from: 5800 MHz to: 5870 MHz ......................................................................... 43

• Added PLL2 DLD programming information and updated the PLLx DLD flowchart graphic .............................................. 44

• Changed PLL1_STORAGE_CELL description from 40-bit thermometer code to 6-bit decimal value ................................ 47

• Clarified CTRL_VCXO represented as PLL1_STORAGE_CELL value .............................................................................. 47

• Changed section from: Low Skew Mode to: Zero Delay Mode (ZDM) ................................................................................ 52

• Changed CLKout7 to CLKout6 and CLKout8 to CLKout9 for zero delay feedback clocks. ................................................ 52

• Changed Set Prop/Store-CP from "fast lock" value to "non-fast lock" value at end of flowchart......................................... 54

• Deleted references to tunable crystal .................................................................................................................................. 55

• Deleted use of external VCO for PLL2................................................................................................................................. 55

• Added register 0x85, 0x86, 0xF6, and 0xAD for PLL2 DLD to recommended programming sequence ............................. 58

• Changed PLL1_PROP from 8 bit to 7 bit field in register map ............................................................................................ 61

• Changed PLL1_PROP_FL from 8 bit to 7 bit field in register map ..................................................................................... 61

• Changed PLL1_STORAGE_CELL 40 bit to 6 bit field. Not a 40 bit thermometer code. Set registers 0x66, 0x67,

0x68, 0x69 to RSRVD in register map ................................................................................................................................ 61

• Changed PLL2_PROP from 8 bit to 6 bit field in register map ............................................................................................ 62

• Changed PLL2_INTG from 8 bit to 5 bit field in register map ............................................................................................. 62

• Added register 0xAC for field PLL1_TSTMODE_REF_FB_EN in register map................................................................... 63

• Added register 0xAD for fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO in register

map....................................................................................................................................................................................... 63

• Added register 0xF6 for PLL2_DLD_EN in register map ..................................................................................................... 63

• Changed channel 7 and 8 to channel 6 and 9 for feedback enable FBBUF_CHx_EN in register map............................... 64

• Deleted unused DEVID values ............................................................................................................................................. 66

• Changed reset value for CHIPID from 0x1 to 0x3................................................................................................................ 66

• Changed reset value for CHIPVER from 0x1 to 0x15 ......................................................................................................... 66

• Changed PLL1_PROP from 8 bit to 7 bit field in register definition .................................................................................... 88

• Changed PLL1_PROP_FL from 8 bit to 7 bit field in register definition .............................................................................. 88

• Deleted 'PLL1 Start-up in Holdover.' text from the PLL1_STARTUP_HOLDOVER_EN bit description .............................. 89

• Changed PLL2_PROP field size from 8 bits to 6 bits in register definition ......................................................................... 93

• Changed PLL2_INTG field from 8 bit to 5 bit field in register 0x80 definition ...................................................................... 95

• Added definition and requirement for setting PLL2_LD_WNDW_SIZE = 0 in register 0x85 definition ............................... 96

• Added definition and requirement for setting PLL2_LD_WNDW_SIZE_INITIAL = 0 in register 0x86 definition.................. 96

LMK04616

ZHCSG70B –MARCH 2017–REVISED JULY 2019

www.ti.com.cn

修修订订历历史史记记录录 (接接下下页页)

• Added note for using PLL1/2 REF/FB(SYS) status output for STAT0 .............................................................................. 100

• Added note for using PLL1/2 REF/FB(SYS) status output for STAT1 .............................................................................. 100

• Added note for using PLL1/2 REF/FB(SYS) status output for SYNC ............................................................................... 103

• Added register 0xAC to register description. New field PLL1_TSTMODE_REF_FB_EN. ................................................. 104

• Added register 0xAD to register description. New fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and

PD_VCO_LDO.................................................................................................................................................................... 104

• Added register 0xF6 to register description. New field PLL2_DLD_EN ............................................................................. 105

• Added register 0xF7 to register description. New field PLL2_DUAL_LOOP_EN .............................................................. 106

• Changed Channel 6 and 9 FBClock Buffers from: Low Skew to: Zero Delay Mode.......................................................... 118

• Changed OUTCH8 and OUTCH7 to OUTCH9 and OUTCH6............................................................................................ 118

• Changed registers for WINDOW SIZE and LOCK COUNT. Updated equation to reflect the more general WINDOW

SIZE and LOCK COUNT names and count frequency. Removed reference to holdover. Updated descriptive text ........ 122

• Updated minimum lock time calculation example to reflect updated register names and count frequency ...................... 122

• Simplified HSDS format description .................................................................................................................................. 127

Changes from Original (March 2017) to Revision A Page

• 将文本从“–70dBc PSRR”更改为“–80dBc PSRR（在 VDDO 上）.......................................................................................... 1

• 将 SPI 接口默认设置从 3 线制更改为 4 线制.......................................................................................................................... 1

• 将 VCO 频率从“5.8GHz 至 6.2GHz”更改为“5.8GHz 至 6.175GHz”........................................................................................ 1

• Changed VCO frequency from: 6200 MHz to: 6175 MHz ...................................................................................................... 5

• Removed tablenote from the doubler input frequency parameter........................................................................................ 12

• Changed VCO tuning range maximum from: 6200 to: 6175 ................................................................................................ 12

• Changed tablenote text from: ATE tested at 2949.12 MHz to: ATE tested at 258-MHz Phase detector frequency............ 12

• Removed tablenote from the output frequency parameter................................................................................................... 14

• Changed output frequency maximum from: 800 MHz to: 1000 MHz .................................................................................. 14

• Added content to the Driving CLKin and OSCin Pins With a Differential Source section.................................................... 30

• Updated Figure 36 ............................................................................................................................................................... 40

• Changed the tuning range of the oscillator from: 6200 MHz to: 6175 MHz ......................................................................... 43

• Updated Figure 48 ............................................................................................................................................................... 53