没有合适的资源?快使用搜索试试~ 我知道了~
TI-LMK04808.pdf
需积分: 5 0 下载量 152 浏览量
2022-11-30
21:49:30
上传
评论 4
收藏 2.11MB PDF 举报
温馨提示
试读
139页
TI-LMK04808.pdf
资源推荐
资源详情
资源评论
FPGA
DAC
Recovered
³GLUW\´FORFNRU
clean clock
0XOWLSOH³FOHDQ´
clocks at different
frequencies
CLKout4, 5, 6, 7
CLKout2
CLKout0, 1
FPGA
CLKin0
Crystal or
VCXO
Backup
Reference
Clock
CLKin1
OSCout0/
OSCout1
CLKout11
CLKout8A
DAC
CLKout9
IF
I
Q
ADC
LMX2541
PLL+VCO
Serializer/
Deserializer
CPLD
LMK0480x
Precision Clock
Conditioner
CLKout3
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
LMK04803
,
LMK04805
,
LMK04806
,
LMK04808
SNAS489K –MARCH 2011–REVISED DECEMBER 2014
LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1 Features 3 Description
The LMK0480x family is the industry's highest
1
• Ultra-Low RMS Jitter Performance
performance clock conditioner with superior clock
– 111 fs RMS Jitter (12 kHz to 20 MHz)
jitter cleaning, generation, and distribution with
– 123 fs RMS Jitter (100 Hz to 20 MHz)
advanced features to meet next generation system
requirements. The dual loop PLLatinum™
• Dual Loop PLLatinum™ PLL Architecture
architecture is capable of 111 fs rms jitter (12 kHz to
• PLL1
20 MHz) using a low noise VCXO module or sub-200
– Integrated Low-Noise Crystal Oscillator Circuit
fs rms jitter (12 kHz to 20 MHz) using a low cost
external crystal and varactor diode.
– Holdover Mode when Input Clocks are Lost
– Automatic or Manual Triggering/Recovery
The dual loop architecture consists of two high-
performance phase-locked loops (PLL), a low-noise
• PLL2
crystal oscillator circuit, and a high-performance
– Normalized PLL Noise Floor of –227 dBc/Hz
voltage controlled oscillator (VCO). The first PLL
– Phase Detector Rate up to 155 MHz
(PLL1) provides low-noise jitter cleaner functionality
while the second PLL (PLL2) performs the clock
– OSCin Frequency-Doubler
generation. PLL1 can be configured to either work
– Integrated Low-Noise VCO
with an external VCXO module or the integrated
• 2 Redundant Input Clocks with LOS
crystal oscillator with an external tunable crystal and
– Automatic and Manual Switch-Over Modes
varactor diode. When paired with a very narrow loop
bandwidth, PLL1 uses the superior close-in phase
• 50 % Duty Cycle Output Divides, 1 to 1045 (Even
noise (offsets below 50 kHz) of the VCXO module or
and Odd)
the tunable crystal to clean the input clock. The
• 12 LVPECL, LVDS, or LVCMOS Programmable
output of PLL1 is used as the clean input reference to
Outputs
PLL2 where it locks the integrated VCO. The loop
bandwidth of PLL2 can be optimized to clean the far-
• Digital Delay: Fixed or Dynamically Adjustable
out phase noise (offsets above 50 kHz) where the
• 25 ps Step Analog Delay Control.
integrated VCO outperforms the VCXO module or
• 14 Differential Outputs. Up to 26 Single Ended.
tunable crystal used in PLL1.
– Up to 6 VCXO/Crystal Buffered Outputs
Device Information
• Clock Rates of up to 1536 MHz
REFERENCE
• 0-Delay Mode
PART NUMBER VCO FREQUENCY
INPUTS
• Three Default Clock Outputs at Power Up
LMK04803 1840 to 2030 MHz
• Multi-Mode: Dual PLL, Single PLL, and Clock
LMK04805 2148 to 2370 MHz
2
Distribution
LMK04806 2370 to 2600 MHz
• Industrial Temperature Range: –40 to 85°C
LMK04808 2750 to 3072 MHz
• 3.15-V to 3.45-V Operation
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
• 2 Dedicated Buffered/Divided OSCin Clocks
• Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
Simplified Schematic
2 Applications
• Data Converter Clocking
• Wireless Infrastructure
• Networking, SONET/SDH, DSLAM
• Medical / Video / Military / Aerospace
• Test and Measurement
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK04803
,
LMK04805
,
LMK04806
,
LMK04808
SNAS489K –MARCH 2011–REVISED DECEMBER 2014
www.ti.com
Table of Contents
8.5 Programming........................................................... 47
1 Features.................................................................. 1
8.6 Register Maps......................................................... 51
2 Applications ........................................................... 1
9 Application and Implementation ........................ 97
3 Description ............................................................. 1
9.1 Application Information............................................ 97
4 Revision History..................................................... 2
9.2 Typical Applications .............................................. 114
5 Pin Configuration and Functions......................... 4
9.3 System Examples ................................................. 122
6 Specifications......................................................... 6
9.4 Do's and Don'ts..................................................... 124
6.1 Absolute Maximum Ratings ...................................... 6
10 Power Supply Recommendations ................... 125
6.2 ESD Ratings.............................................................. 6
10.1 Pin Connection Recommendations..................... 125
6.3 Recommended Operating Conditions....................... 6
10.2 Current Consumption and Power Dissipation
6.4 Thermal Information.................................................. 7
Calculations............................................................ 126
6.5 Electrical Characteristics........................................... 7
11 Layout................................................................. 129
6.6 Timing Requirements.............................................. 13
11.1 Layout Guidelines ............................................... 129
6.7 Typical Characteristics: Clock Output AC
11.2 Layout Example .................................................. 130
Characteristics ......................................................... 14
12 Device and Documentation Support ............... 131
7 Parameter Measurement Information ................ 15
12.1 Device Support.................................................... 131
7.1 Charge Pump Current Specification Definitions...... 15
12.2 Documentation Support ...................................... 131
7.2 Differential Voltage Measurement Terminology...... 16
12.3 Related Links ...................................................... 131
8 Detailed Description............................................ 17
12.4 Trademarks......................................................... 131
8.1 Overview ................................................................. 17
12.5 Electrostatic Discharge Caution.......................... 131
8.2 Functional Block Diagram ....................................... 21
12.6 Glossary.............................................................. 131
8.3 Feature Description................................................. 22
13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes........................................ 43
Information ......................................................... 131
4 Revision History
Changes from Revision J (March 2013) to Revision K Page
• Changed 90 to 80 and 80 to 90 for f
CLKout-startup
parameter in Electrical Characteristics....................................................... 11
• Added "Specification is not valid for CLKoutX or CLKoutY in analog delay mode " in table note for Electrical
Characteristics ..................................................................................................................................................................... 11
• Changed "Temperature" to "Ambient Temperature" in heading titled "Charge Pump Output Current Magnitude
Variation vs. Ambient Temperature" .................................................................................................................................... 15
• Added "temporarily" in VCXO/CRYSTAL Buffered Outputs ................................................................................................ 18
• Changed from "n possible" to "D possible" in 0-Delay ......................................................................................................... 20
• Changed "can" to "cannot" in Input Clock Switching - Pin Select Mode .............................................................................. 24
• Deleted Clock Switch Event without Holdover in Clock Switch Event with Holdover .......................................................... 25
• Added paragraph beginning "For applications ..." in PLL2 Frequency Doubler................................................................... 29
• Changed 5 to15 in Table 11 ................................................................................................................................................. 42
• Deleted Mode 5 row in Table 12 .......................................................................................................................................... 43
• Added Mode 15 Additional Configurations section .............................................................................................................. 46
• In Table 16, added [27:26], [23:22], and [21:20] for Register 27 row. Added [31:20] for R28. Added [26:24] for R30.
Added [7:6]. .......................................................................................................................................................................... 51
• In Table 18, changed "Actual PLL2 N divider value used in calibration routine". Added footnote "Inversion for Status
0 and 1 pins is only valid for CLKin_SELECT_MODE = 0x06"............................................................................................ 56
• In Table 28, added "to reduce supply..." footnote for 9 through 14. Added footnote "To reduce supply switching and
crosstalk noise, it is recommended to use a complementary LVCMOS output type such as 6 or 7". ................................. 64
• Added footnote "To reduce supply" for 8 through 14 in Table 32 ....................................................................................... 66
• Changed "Divide" to "Definition" in Table 39, Table 40, Table 61, and Table 62 ................................................................ 68
• Changed to "MUX OUTPUT" in Table header row in Table 42............................................................................................ 69
• In Table 43, added footnote, "Contact TI Applications for more information on using this mode". Changed to "Dual
2 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808
LMK04803
,
LMK04805
,
LMK04806
,
LMK04808
www.ti.com
SNAS489K –MARCH 2011–REVISED DECEMBER 2014
Revision History (continued)
PLL, External VCO (Fin), 0-Delay" for 15 (0x0F) ................................................................................................................. 70
• Added "Inversion for Status 0 and 1 pins is only valid for CLKin_SELECT_MODE = 0x06" in CLKin_Sel_INV................. 78
• In FORCE_HOLDOVER, added "(EN_TRACK = 0 or 1, EN_MAN_DAC =1)". Added "(EN_TRACK = 1,
EN_MAN_DAC = 0, EN_VTUNE_RAIL_DET = 0)".............................................................................................................. 82
• Changed to R[23:14] in DAC_CNT....................................................................................................................................... 83
• In Table 90, added (0x0000), (0x0001), (0x0002), (0x0003). Changed "Divide" to "Value" in the header row. .................. 87
• Added (0x00) through (0x04) in Table 91............................................................................................................................. 88
• Added PLL2 Frequency Doubler .......................................................................................................................................... 88
• Changed from "Divide" to "Value" in Table 95 ..................................................................................................................... 89
• Added PLL2 Frequency Doubler reference in Table 103..................................................................................................... 92
• Added note "Unless in 0-delay... " in PLL2_N_CAL, PLL2 N Calibration Divider ................................................................ 93
• Changed "Mode_MUX1" to "VCO_MUX" in PLL2_P, PLL2 N Prescaler Divider................................................................. 94
• Changed "register" to "Defintion" in table header row for Table 110 ................................................................................... 95
• Updated Minimum Digital Lock Detect Time Calculation Example ................................................................................... 107
• Added "Performance of other LMK0480x devices will be similar" in Optional Crystal Oscillator Implementation
(OSCin/OSCin*).................................................................................................................................................................. 110
• Changed to "(fs rms)" in Table 125 ................................................................................................................................... 111
• Added text in red for Figure 40 .......................................................................................................................................... 123
• In Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs), added bullet point starting with "It is recommended..."
Changed ≤ 10 MHz to ≤ 30 MHz........................................................................................................................................ 125
• Added paragraph "It is recommended..." in Vcc5 (CLKin and OSCout1), Vcc7 (OSCin and OSCout0) ........................... 126
• Added Mode = 15. Removed Mode = 5 in Table 127 ........................................................................................................ 127
• Deleted "of about 2 square inches" in Layout Guidelines .................................................................................................. 129
Changes from Revision I (March 2013) to Revision J Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808
CLKout8
CLKout9
CLKout10*
Status_CLKin0
CLKout8*
CLKout9*
Vcc12
CLKout10
CLKout11*
CLKout11
Status_CLKin1
Vcc13
DAP
Top Down View
CLKout6*
Vcc11
CLKout7*
CLKout7
OSCout1*
Vcc2
Vcc3
CLKout4
Vcc4
CLKout4*
CLKout5*
CLKout5
GND
FBCLKin/Fin/CLKin1
FBCLKin*/Fin*/CLKin1*
Status_Holdover
CLKin0
CLKin0*
Vcc5
OSCout1
Vcc7
CPout2
Vcc9
CLKuWire
OSCin*
OSCout0
OSCout0*
Vcc8
LEuWire
DATAuWire
Vcc10
CLKout6
CPout1
Status_LD
Vcc6
OSCin
CLKout3
CLKout0
CLKout0*
CLKout1*
NC
CLKout1
NC
SYNC
NC
NC
Vcc1
LDObyp1
LDObyp2
CLKout2
CLKout2*
CLKout3*
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
1918 20 21 22 23 24 25 26 27 28 29 30 31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
6263 61
60 59
58
57
56 55
54
53 52
51 50 49
LMK04803
,
LMK04805
,
LMK04806
,
LMK04808
SNAS489K –MARCH 2011–REVISED DECEMBER 2014
www.ti.com
5 Pin Configuration and Functions
64-Pin WQFN with Exposed Pad
NKD Package
(Top View)
Pin Functions
(1)
PIN
I/O TYPE DESCRIPTION
NUMBER NAME
1, 2 CLKout0, CLKout0* O Programmable Clock output 0 (clock group 0).
3, 4 CLKout1*, CLKout1 O Programmable Clock output 1 (clock group 0).
6 SYNC I/O Programmable CLKout Synchronization input or programmable status pin.
5, 7, 8, 9 NC – – No Connection. These pins must be left floating.
10 Vcc1 PWR Power supply for VCO LDO.
11 LDObyp1 ANLG LDO Bypass, bypassed to ground with 10 µF capacitor.
12 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 µF capacitor.
13, 14 CLKout2, CLKout2* O Programmable Clock output 2 (clock group 1).
15, 16 CLKout3*, CLKout3 O Programmable Clock output 3 (clock group 1).
17 Vcc2 PWR Power supply for clock group 1: CLKout2 and CLKout3.
18 Vcc3 PWR Power supply for clock group 2: CLKout4 and CLKout5.
(1) See Pin Connection Recommendations.
4 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808
LMK04803
,
LMK04805
,
LMK04806
,
LMK04808
www.ti.com
SNAS489K –MARCH 2011–REVISED DECEMBER 2014
Pin Functions
(1)
(continued)
PIN
I/O TYPE DESCRIPTION
NUMBER NAME
19, 20 CLKout4, CLKout4* O Programmable Clock output 4 (clock group 2).
21, 22 CLKout5*, CLKout5 O Programmable Clock output 5 (clock group 2).
23 GND PWR Ground.
24 Vcc4 PWR Power supply for digital.
CLKin1, CLKin1* Reference Clock Input Port 1 for PLL1. AC or DC Coupled.
Feedback input for external clock feedback input (0-delay
FBCLKin, FBCLKin*
25, 26 I ANLG mode). AC or DC Coupled.
External VCO input (External VCO mode). AC or DC
Fin/Fin*
Coupled.
Programmable status pin, default readback output.
27 Status_Holdover I/O Programmable Programmable to holdover mode indicator. Other options
available by programming.
Reference Clock Input Port 0 for PLL1.
28, 29 CLKin0, CLKin0* I ANLG
AC or DC Coupled.
30 Vcc5 PWR Power supply for clock inputs and OSCout1.
31, 32 OSCout1, OSCout1* O LVPECL Buffered output 1 of OSCin port.
Programmable status pin, default lock detect for PLL1 and
33 Status_LD I/O Programmable
PLL2. Other options available by programming.
34 CPout1 O ANLG Charge pump 1 output.
35 Vcc6 PWR Power supply for PLL1, charge pump 1.
Feedback to PLL1, Reference input to PLL2.
36, 37 OSCin, OSCin* I ANLG
AC Coupled.
38 Vcc7 PWR Power supply for OSCin, OSCout0, and PLL2 circuitry.
(2)
39, 40 OSCout0, OSCout0* O Programmable Buffered output 0 of OSCin port.
(2)
41 Vcc8 PWR Power supply for PLL2, charge pump 2.
42 CPout2 O ANLG Charge pump 2 output.
43 Vcc9 PWR Power supply for PLL2.
44 LEuWire I CMOS MICROWIRE Latch Enable Input.
45 CLKuWire I CMOS MICROWIRE Clock Input.
46 DATAuWire I CMOS MICROWIRE Data Input.
47 Vcc10 PWR Power supply for clock group 3: CLKout6 and CLKout7.
48, 49 CLKout6, CLKout6* O Programmable Clock output 6 (clock group 3).
50, 51 CLKout7*, CLKout7 O Programmable Clock output 7 (clock group 3).
52 Vcc11 PWR Power supply for clock group 4: CLKout8 and CLKout9.
53, 54 CLKout8, CLKout8* O Programmable Clock output 8 (clock group 4).
55, 56 CLKout9*, CLKout9 O Programmable Clock output 9 (clock group 4).
57 Vcc12 PWR Power supply for clock group 5: CLKout10 and CLKout11.
CLKout10,
58, 59 O Programmable Clock output 10 (clock group 5).
CLKout10*
CLKout11*,
60, 61 O Programmable Clock output 11 (clock group 5).
CLKout11
Programmable status pin. Default is input for pin control of
62 Status_CLKin0 I/O Programmable PLL1 reference clock selection. CLKin0 LOS status and
other options available by programming.
Programmable status pin. Default is input for pin control of
63 Status_CLKin1 I/O Programmable PLL1 reference clock selection. CLKin1 LOS status and
other options available by programming.
64 Vcc13 PWR Power supply for clock group 0: CLKout0 and CLKout1.
DAP DAP – GND DIE ATTACH PAD, connect to GND.
(2) See Vcc5 (CLKin and OSCout1), Vcc7 (OSCin and OSCout0) for information on configuring device for optimum performance.
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808
剩余138页未读,继续阅读
资源评论
不觉明了
- 粉丝: 3230
- 资源: 5614
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- 藏区特产销售平台源代码+论文+毕业设计.zip
- B297C8EC5A69641DB3E681E1B3F894E5.mp4
- PrimitivesPro v2.2.unitypackage
- 财务管理系统源代码+论文.zip
- 高级信息通信运行管理员第七套试卷
- UModeler v2.11.6 (May 10, 2024).unitypackage
- 基于Selenium的Java爬虫实战(内含谷歌浏览器Chrom和Chromedriver版本127.0.6486.0)
- 基于FPGA的CORDIC算法旋转模式实现
- bilibili视频解析下载源码
- 基于Selenium的Java爬虫实战(内含谷歌浏览器Chrom和Chromedriver版本124.0.6367.60)
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功