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SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Independent Asynchronous Inputs and
Outputs
D
Low-Power Advanced CMOS Technology
D
Bidirectional
D
Dual 1024 by 9 Bits
D
Programmable Almost-Full/Almost-Empty
Flag
D
Empty, Full, and Half-Full Flags
D
Access Times of 25 ns With a 50-pF Load
D
Data Rates up to 50 MHz
D
Fall-Through Times of 22 ns Maximum
D
High Output Drive for Direct Bus Interface
D
Package Options Include 44-Pin Plastic
Leaded Chip Carriers (FN) and 64-Pin Thin
Quad Flat (PAG, PM) Packages
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2235 is arranged as two 1024 × 9-bit FIFOs for high speed and fast access times.
It processes data at rates up to 50 MHz, with access times of 25 ns in a bit-parallel format.
The SN74ACT2235 consists of bus-transceiver circuits, two 1024 × 9-bit FIFOs, and control circuitry arranged
for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable (GAB
and GBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 2 shows the eight fundamental bus-management functions that can be performed with the
SN74ACT2235.
For more information on this device family, see the application report, 1K × 9 × 2 Asynchronous FIFO
SN74ACT2235, literature number SCAA010.
The SN74ACT2235 is characterized for operation from 0°C to 70°C.
B2
B3
B4
V
CC
B5
B6
B7
B8
GND
AF/AEB
HFB
39
38
37
36
35
34
33
32
31
30
29
18 19
7
8
9
10
11
12
13
14
15
16
17
A3
A4
V
CC
A5
A6
A7
A8
GND
AF/AEA
HFA
LDCKA
20 21 22 23
FN PACKAGE
(TOP VIEW)
GAB
GND
B0
B1
543 21644
A2
A1
A0
GND
GBA
SBA
SAB
EMPTYA
UNCKA
FULLB
LDCKB
FULLA
UNCKB
EMPTYB
DAF
RSTA
RSTB
DBF
42 41 4043
24 25 26 27 28
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
CC
V
CC
A3
A4
V
CC
GND
GND
A5
A6
V
CC
V
CC
A7
A8
GND
GND
AF/AEA
HFA
A1
A0
GND
GBA
A2
GND
SBA
GND
B1
B2
SAB
B0
EMPTYB
UNCKA
FULLA
DAF
EMPTYA
LDCKB
NC
NC
LDCKA
NC
FULLB
RSTB
DBF
UNCKB
RSTA
NC
GND
GAB
17 18 19 20 21 22 25 26 27 28 29 30 31 322423
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PAG OR PM PACKAGE
(TOP VIEW)
NC
V
CC
B3
B4
GND
GND
V
CC
B5
B6
V
CC
B7
B8
GND
GND
AF/AEB
HFB
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
26
UNCKA
LDCKA
A1
24
DEF B FLAG
20
EMPTYB
DEF A FLAG
21
EMPTYA
25
FULLA
18
17
LDCKA
UNCKA
Reset A
22
EN2
2
GBA
EN1
43
GAB
0
1
SBA
1
44
SAB
27
FULL B
UNCKB
19
LDCKB
28
23
RESET B
LDCKB
UNCKB
Φ
FIFO
1024 × 9 × 2
SN74ACT2235
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
40
39
38
37
35
34
33
5
6
7
8
10
11
12
A8
13
B8
32
MODE
ALMOST-FULL/
15
AF/AEA
ALMOST-EMPTY A
AF/AEB
30
ALMOST-FULL/
ALMOST-EMPTY A
0
4
A0
B0
41
0
8
8
A Data
B Data
HALF-FULL A
16
HFA HFB
29
HALF-FULL B
RSTA
DAF
FULLA
EMPTYA
RSTB
DBF
FULLB
EMPTYB
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.

SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
Q
D
B0
Q
D
One of Nine Channels
SAB
SBA
EMPTYB
UNCKB
GBA
GAB
RSTA
DAF
FULLA
LDCKA
A0
RSTB
DBF
FULLB
LDCKB
To Other Channels
One of Nine Channels
To Other Channels
EMPTYA
UNCKA
AF/AEA
AF/AEB
HFB
Φ
FIFO A
1024 × 9
HFA
Φ
FIFO B
1024 × 9
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