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SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Low-Power Advanced CMOS Technology
D
Load and Unload Clocks Can Be
Asynchronous or Coincident
D
1024 Words × 18 Bits
D
Programmable Almost-Full/Almost-Empty
Flag
D
Empty, Full, and Half-Full Flags
D
Fast Access Times of 30 ns With a 50-pF
Load
D
Fall-Through Time Is 20 ns Typical
D
Data Rates up to 40 MHz
D
High-Output Drive for Direct Bus Interface
D
3-State Outputs
D
Package Options Include 68-Pin (FN) and
80-Pin Thin Quad Flat (PN) Packages
28 29
V
CC
Q14
Q13
GND
Q12
Q11
V
CC
Q10
Q9
GND
Q8
Q7
V
CC
Q6
Q5
GND
Q4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
D14
D13
D12
D11
D10
D9
V
CC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
31 32 33 34
FN PACKAGE
(TOP VIEW)
V
GND
87 65493
D17
GND
UNCK
NC
NC
OE
RESET
HF
V
Q0
Q1
LDCK
NC
NC
AF/AE
GND
FULL
168672
35 36 37 38 39
66 65
27
DAF
GND
EMPTY
V
64 63 62 61
40 41 42 43
GND
Q2
Q3
V
Q17
Q16
GND
Q15
D15
D16
CC
CC
CC
CC
NC – No internal connection
V
CC
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.

SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
22 23
V
CC
V
CC
NC
Q3
Q2
GND
Q1
Q0
V
CC
HF
FULL
GND
GND
AF/AE
V
CC
NC
NC
LDCK
GND
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
GND
GND
Q16
Q17
V
CC
EMPTY
GND
V
CC
RESET
OE
NC
NC
UNCK
GND
D17
D16
D15
NC
NC
25 26 27 28
PN PACKAGE
(TOP VIEW)
Q9
79 78 77 76 7580 74
Q14
Q13
GND
GND
Q12
Q11
Q10
D7
D5
D13
D12
D11
D10
D9
D8
72 71 7073
29
30 31 32 33
69 68
21
NC
Q8
67 66 65 64
34 35 36 37
D4
D3
D2
D1
Q7
Q6
Q5
Q15
D0
DAF
38 39 40
GND
GND
63 62 61
V
CC
GND
Q4
CC
V
D14
D6
NC
GND
V
CC
NC – No internal connection
V
CC
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7802 is a 1024-word by 18-bit FIFO for high-speed applications. It processes data
in a bit-parallel format at rates up to 40 MHz and access times of 30 ns.
Data is written into the FIFO memory on a low-to-high transition on the load-clock (LDCK) input and is read out
on a low-to-high transition on the unload-clock (UNCK) input. The memory is full when the number of words
clocked in exceeds by 1024 the number of words clocked out. When the memory is full, LDCK has no effect on
the data in the memory; when the memory is empty, UNCK has no effect.
A low level on the reset (RESET
) input resets the FIFO internal clock stack pointers and sets full (FULL) high,
almost full/almost empty (AF/AE) high, half full (HF) low, and empty (EMPTY
) low. The Q outputs are not reset
to any specific logic level. The FIFO must be reset upon power up. The Q outputs are noninverting and are in
the high-impedance state when the output-enable (OE) input is low.
When writing to the FIFO after a reset pulse or when the FIFO is empty, the first active transition on LDCK drives
EMPTY
high and causes the first word written to the FIFO to appear on the Q outputs. An active transition on
UNCK is not required to read the first word written to the FIFO. Each subsequent read from the FIFO requires
an active transition on UNCK.
The SN74ACT7802 can be cascaded in the word-width direction but not in the word-depth direction.
The SN74ACT7802 is characterized for operation from 0°C to 70°C.

SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
UNCK
14
D10
13
D11
12
D12
11
D13
10
D14
9
D15
8
D16
17
7
D17
RESET
1
29
LDCK
5
UNCK
LDCK
EN1
2
OE
0
26
D0
25
D1
24
D2
23
D3
22
D4
21
D5
20
D6
19
D7
17
D8
15
D9
Data
Q0
38
0
Q1
39
Q2
41
Q3
42
Q4
44
35
FULL
HF
36
HALF FULL
AF/AE
33
ALMOST FULL/EMPTY
66
EMPTY
Q15
61
Q16
63
Q17
64
17
Q5
46
Q6
47
Q7
49
Q8
50
Q9
52
Q10
53
Q11
55
Q12
56
Q13
58
Q14
59
Data
1
DEF ALMOST FULL
27
Φ
FIFO 1024 × 18
SN74ACT7802
RESET
DAF
FULL
EMPTY
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
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