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SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Load Clock and Unload Clock Can Be
Asynchronous or Coincident
D
512 Words by 18 Bits
D
Low-Power Advanced CMOS Technology
D
Full, Empty, and Half-Full Flags
D
Programmable Almost-Full/Almost-Empty
Flag
D
Fast Access Times of 15 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
D
Data Rates up to 50 MHz
D
3-State Outputs
D
Pin-to-Pin Compatible With SN74ACT7806
and SN74ACT7814
D
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
description
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ACT7804 is a
512-word by 18-bit FIFO for high speed and fast
access times. It processes data at rates up to
50 MHz and access times of 15 ns in a bit-parallel
format.
Data is written into memory on a low-to-high
transition at the load-clock (LDCK) input and is
read out on a low-to-high transition at the
unload-clock (UNCK) input. The memory is full
when the number of words clocked in exceeds the
number of words clocked out by 512. When the
memory is full, LDCK signals have no effect on the
data residing in memory. When the memory is
empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL
), empty (EMPTY), half-full (HF), and
almost-full/almost-empty (AF/AE) flags. The FULL
output is low when the memory is full and high when the
memory is not full. The EMPTY
output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 256 or more words. The AF/AE status flag is a programmable flag. The
first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value
(X) and the almost-full offset value (Y) if program enable (PEN
) is low. The AF/AE flag is high when the FIFO
contains X or fewer words or (512 – Y) or more words. The AF/AE flag is low when the FIFO contains between
(X + 1) and (511 – Y) words.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments Incorporated.
1
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9
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14
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16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET
D17
D16
D15
D14
D13
D12
D11
D10
V
CC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
LDCK
NC
NC
FULL
OE
Q17
Q16
Q15
GND
Q14
V
CC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
CC
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY
DL PACKAGE
(TOP VIEW)
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF
low, and EMPTY
low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon
power up.
The first word loaded into empty memory causes EMPTY
to go high and the data to appear on the Q outputs.
It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with
respect to the data inputs and are in the high-impedance state when the output-enable (OE
) input is high.
The SN74ACT7804 is characterized for operation from 0°C to 70°C.
logic symbol
†
0
21
D0
20
D1
19
D2
18
D3
17
D4
16
D5
15
D6
14
D7
12
D8
Q0
33
0
Q1
34
Q2
36
Q3
37
Q4
38
28
FULL
HF
22
HALF-FULL
AF/AE
24
ALMOST FULL/EMPTY
29
EMPTY
Q5
40
Q6
41
Q7
42
Q8
43
Data
1
Φ
FIFO 512 × 18
SN74ACT7804
11
D9
9
D10
8
D11
7
D12
6
D13
5
D14
4
D15
3
D16
17
2
D17
Q9
45
Q10
46
Q11
47
Q12
48
Q13
49
Q14
51
Q15
53
Q16
54
Q17
55
17
RESET
OE
PEN
RESET
1
25
LDCK
LDCK
Data
PROGRAM ENABLE
23
EN1
56
32
UNCK
UNCK
FULL
EMPTY
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Q0–Q17
AF/AE
HF
OE
D0–D17
UNCK
LDCK
RESET
PEN
EMPTY
FULL
Status-
Flag
Logic
Read
Pointer
Reset
Logic
Location 1
Location 2
Location 511
Location 512
512 × 18 SRAM
Write
Pointer
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AF/AE 24 O
Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when
memory contains X or fewer words or (512 – Y) or more words. AF/AE is high after reset.
D0–D17
2–9, 11–12,
14–21
I 18-bit data input port
EMPTY 29 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL 28 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 22 O Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.
LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.
PEN
23 I
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7
is latched as an AF/AE offset value when PEN
is low and LDCK is high.
Q0–Q17
33–34, 36–38,
40–43, 45–49,
51, 53–55
O 18-bit data output port
RESET
1 I Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low.
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
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