没有合适的资源?快使用搜索试试~ 我知道了~
资源推荐
资源详情
资源评论












SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Designed to Be Used in Level-Shifting
Applications
description/ordering information
The SN74CBTD3861 provides ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay. A diode to V
CC
is integrated on the die to
allow for level shifting from 5-V signals at the
device inputs to 3.3-V signals at the device
outputs.
The device is organized as one 10-bit switch with
a single output-enable (OE
) input. When OE is
low, the switch is on, and port A is connected to
port B. When OE
is high, the switch is open, and
the high-impedance state exists between the two
ports.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC DW
Tube SN74CBTD3861DW
CBTD3861
SOIC
–
DW
Tape and reel SN74CBTD3861DWR
CBTD3861
40°Cto85°C
SSOP – DB Tape and reel SN74CBTD3861DBR CC861
–
40°C
to
85°C
SSOP (QSOP) – DBQ Tape and reel SN74CBTD3861DBQR CBTD3861
TSSOP – PW Tape and reel SN74CBTD3861PWR CC861
TVSOP – DGV Tape and reel SN74CBTD3861DGVR CC861
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT
OE
FUNCTION
L A port = B port
H Disconnect
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
A1
B1
A10
B10
OE
2
11
23
22
13
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I/O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBQ package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level control input voltage 2 V
V
IL
Low-level control input voltage 0.8 V
T
A
Operating free-air temperature –40 85 °C
In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting
effect.
NOTE 3: All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IK
V
CC
= 4.5 V, I
I
= –18 mA –1.2 V
V
OH
See Figure 2
I
I
V
CC
= 5.5 V, V
I
= 5.5 V or GND ±1 µA
I
CC
V
CC
= 5.5 V, I
O
= 0, V
I
= V
CC
or GND 1.5 mA
∆I
CC
‡
Control inputs V
CC
= 5.5 V, One input at 3.4 V, Other inputs at V
CC
or GND 2.5 mA
C
i
Control inputs V
I
= 3 V or 0 2.5 pF
C
io(OFF)
V
O
= 3 V or 0, OE = V
CC
4 pF
§
V
I
=0
I
I
= 64 mA 5 7
r
on
§
V
CC
= 4.5 V
V
I
=
0
I
I
= 30 mA 5 7
Ω
V
I
= 2.4 V, I
I
= 15 mA 20 50
†
All typical values are at V
CC
= 5 V, T
A
= 25°C.
‡
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
§
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN MAX UNIT
t
pd
¶
A or B B or A 0.35 ns
t
en
OE
A or B 2.6 10 ns
t
dis
OE
A or B 1 6 ns
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

SN74CBTD3861
10-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS084G – JULY 1998 – REVISED JULY 2002
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
V
OH
V
OL
0 V
V
OL
+ 0.3 V
V
OH
– 0.3 V
0 V
Input
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
7 V
Open
TEST S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
≤ 2.5 ns, t
f
≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
剩余16页未读,继续阅读
资源评论

不觉明了
- 粉丝: 616
- 资源: 3489

上传资源 快速赚钱
我的内容管理 收起
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助

会员权益专享
安全验证
文档复制为VIP权益,开通VIP直接复制
