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SCBS782A − NOVEMBER 2003 − JULY 2006
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
†
D Member of the Texas Instruments
Widebus Family
D A-Port Outputs Have Equivalent 22-Ω
Series Resistors, So No External Resistors
Are Required
D Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
D Supports Unregulated Battery Operation
Down to 2.7 V
D Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
D I
off
and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74LVTH162245 is a 16-bit (dual-octal) noninverting 3-state transceiver designed for low-voltage (3.3-V)
V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. The device allows data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE
) input can be used to disable the device so that the buses effectively are
isolated.
Copyright 2006 Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#'
+&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$
$#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+'
#'$#0 "** (""!'#'$
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE

SCBS782A − NOVEMBER 2003 − JULY 2006
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors
to reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE
should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − DGG Tape and reel CLVTH162245IDGGREP LH162245EP
−55°C to 125°C SSOP − DL Tape and reel CLVTH162245MDLREP LVTH162245EP
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE DIR
OPERATION
L L B data to A bus
L H A data to B bus
H X Isolation
logic diagram (positive logic)
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13

SCBS782A − NOVEMBER 2003 − JULY 2006
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
−0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1) −0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, I
O
: B port 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A port 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): B port 64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A port 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 95°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V
O
> V
CC
.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
recommended operating conditions (see Note 5)
MIN MAX UNIT
V
CC
Supply voltage 2.7 3.6 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 5.5 V
I
OH
High-level output current
A port −12
mA
I
OH
High-level output current
B port
−32
mA
I
OL
Low-level output current
A port 12
mA
I
OL
Low-level output current
B port
64
mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 µs/V
T
A
Operating free-air temperature
SN74LVTH162245I −40 85
°C
T
A
Operating free-air temperature
SN74LVTH162245M −55 125
°
C
NOTE 5: All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).

SCBS782A − NOVEMBER 2003 − JULY 2006
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IK
V
CC
= 2.7 V, I
I
= −18 mA −1.2 V
A port
V
CC
= 2.7 V to 3.6 V, I
OH
= −100 µA V
CC
− 0.2
A port
V
CC
= 3 V, I
OH
= −12 mA 2
V
OH
V
CC
= 2.7 V to 3.6 V, I
OH
= −100 µA V
CC
− 0.2
V
V
OH
B port
V
CC
= 2.7 V, I
OH
= −8 mA 2.4
V
B port
V
CC
= 3 V, I
OH
= −32 mA 2
A port
V
CC
= 2.7 V to 3.6 V, I
OL
= 100 µA 0.2
A port
V
CC
= 3 V, I
OL
= 12 mA 0.8
V
CC
= 2.7 V
I
OL
= 100 µA 0.2
V
OL
V
CC
= 2.7 V
I
OL
= 24 mA 0.5
V
V
OL
B port
I
OL
= 16 mA 0.4
V
B port
V
CC
= 3 V
I
OL
= 32 mA 0.5
V
CC
= 3 V
I
OL
= 64 mA 0.55
Control inputs
V
CC
= 3.6 V, V
I
= V
CC
or GND ±1
Control inputs
V
CC
= 0 V or 3.6 V, V
I
= 5.5 V 10
I
I
V
I
= 5.5 V 20
µA
I
I
A or B port
‡
V
CC
= 3.6 V
V
I
= V
CC
5
µA
A or B port
‡
V
CC
= 3.6 V
V
I
= 0 −10
I
off
V
CC
= 0 V, V
I
or V
O
= 0 to 4.5 V ±100 µA
V
CC
= 3 V
V
I
= 0.8 V 75
I
I(hold)
A or B port
V
CC
= 3 V
V
I
= 2 V −75
µA
I
I(hold
)
A or B port
V
CC
= 3.6 V
§
, V
I
= 0 to 3.6 V
500
−750
µ
A
I
OZPU
V
CC
= 0 to 1.5 V, V
O
= 0.5 V to 3 V, OE = don’t care ±100 µA
I
OZPD
V
CC
= 1.5 V to 0 V, V
O
= 0.5 V to 3 V, OE = don’t care ±100 µA
V
CC
= 3.6 V, I
O
= 0 V,
Outputs high 0.19
I
CC
V
CC
= 3.6 V, I
O
= 0 V,
V
I
= V
CC
or GND
Outputs low 5
mA
I
CC
V
I
= V
CC
or GND
Outputs disabled 0.19
mA
∆I
CC
¶
V
CC
= 3 V to 3.6 V, One input at
V
CC
− 0.6 V, Other inputs at
SN74LVTH162245I 0.2
mA
∆I
CC
¶
CC
V
CC
− 0.6 V, Other inputs at
V
CC
or GND
SN74LVTH162245M 0.3
mA
C
i
V
I
= 3 V or 0 V 4 pF
C
io
V
O
= 3 V or 0 V 10 pF
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
‡
Unused pins at V
CC
or GND
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
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